iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22	1	-1/+1
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22	1	-0/+23
*	Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option	Clifford Wolf	2014-02-22	2	-1/+17
*	Made MiniSat solver backend configurable in ezminisat.h	Clifford Wolf	2014-02-22	2	-3/+10
*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21	1	-2/+6
*	Added vhdl2verilog	Clifford Wolf	2014-02-21	2	-0/+155
*	Progress in presentation	Clifford Wolf	2014-02-21	6	-32/+113
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21	1	-21/+27
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21	1	-2/+4
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21	1	-4/+4
*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21	8	-0/+215
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21	1	-17/+65
*	Progress in presentation	Clifford Wolf	2014-02-21	5	-19/+177
*	Progress in presentation	Clifford Wolf	2014-02-20	4	-11/+51
*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20	1	-4/+21
*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20	1	-0/+79
*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20	1	-10/+30
*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20	2	-8/+49
*	Progress in presentation	Clifford Wolf	2014-02-20	5	-0/+207
*	Added connwrappers command	Clifford Wolf	2014-02-20	2	-0/+206
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20	1	-6/+7
*	Progress in presentation	Clifford Wolf	2014-02-20	10	-10/+152
*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19	2	-0/+170
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-18	2	-50/+99
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\| *	Added "sat -dump_cnf"	Clifford Wolf	2014-02-18	1	-5/+34
\| *	Coding style corrections in SatHelper::dump_model_to_vcd()	Clifford Wolf	2014-02-18	1	-31/+31
\| *	Improved non-verbose ezSAT::printDIMACS() format	Clifford Wolf	2014-02-18	1	-1/+6
\| *	Added "sat -initsteps"	Clifford Wolf	2014-02-18	1	-14/+29
* \|	Progress in presentation	Clifford Wolf	2014-02-18	6	-3/+72
* \|	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18	1	-0/+39
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	8	-8/+31
*	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups	Clifford Wolf	2014-02-17	1	-5/+9
*	Added "-dump_fail_to_vcd" argument to SAT solver	Andrew Zonenberg	2014-02-17	1	-0/+114
*	Progress in presentation	Clifford Wolf	2014-02-17	3	-9/+37
*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17	1	-12/+12
*	Progress in presentation	Clifford Wolf	2014-02-16	5	-1/+80
*	Added some additional checks to techmap	Clifford Wolf	2014-02-16	1	-0/+14
*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16	1	-0/+23
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16	1	-2/+2
*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16	1	-0/+5
*	Progress in presentation	Clifford Wolf	2014-02-16	5	-1/+79
*	Fixed use of selection in splitnets command	Clifford Wolf	2014-02-16	1	-1/+1
*	Added recursion support to techmap	Clifford Wolf	2014-02-16	1	-260/+262
*	Progress in presentation	Clifford Wolf	2014-02-16	6	-3/+74
*	Progress in presentation	Clifford Wolf	2014-02-16	6	-1/+114
*	Improved support for constant functions	Clifford Wolf	2014-02-16	1	-1/+50
*	Now we are in Yoys 0.2.0+ development	Clifford Wolf	2014-02-16	2	-3/+9
*	Tagging Yoys 0.2.0	Clifford Wolf	2014-02-16	2	-5/+88
*	Added != support for relational select pattern	Clifford Wolf	2014-02-16	1	-1/+7
*	Added iopadmap -bits	Clifford Wolf	2014-02-15	1	-14/+48