iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Improved FSM tests	Clifford Wolf	2014-08-08	4	-2/+5
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*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08	1	-0/+4
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*	Fixed "fsm -export"	Clifford Wolf	2014-08-08	2	-6/+5
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*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08	1	-0/+13
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*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08	1	-8/+25
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*	Added FSM test bench	Clifford Wolf	2014-08-08	2	-0/+113
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*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08	1	-2/+16
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*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07	6	-16/+24
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*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07	1	-2/+2
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*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07	1	-3/+5
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*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07	2	-1/+32
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	5	-6/+80
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*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
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*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-29/+47
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*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05	1	-3/+2
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	4	-12/+93
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*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-47/+77
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*	Added mux support to wreduce command	Clifford Wolf	2014-08-05	1	-36/+82
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	4	-9/+90
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*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05	2	-3/+16
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*	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04	2	-1/+12
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	2	-9/+21
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*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03	1	-0/+7
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*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03	3	-2/+3
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*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03	1	-43/+16
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*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03	2	-0/+253
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*	Added query() API to ModIndex	Clifford Wolf	2014-08-03	1	-8/+46
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*	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03	1	-0/+3
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03	2	-17/+63
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*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
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*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02	1	-5/+40
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*	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02	1	-4/+3
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*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02	1	-2/+3
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*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02	1	-3/+19
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	2	-10/+17
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	3	-8/+7
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	16	-37/+37
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	10	-44/+60
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*	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02	2	-2/+9
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	5	-33/+65
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*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02	1	-2/+6
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	2	-15/+90
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*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02	1	-2/+2
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	33	-261/+237
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	12	-32/+71
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*	Added logfile hash to statistics footer	Clifford Wolf	2014-08-01	5	-45/+79
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	8	-283/+334
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*	Added per-pass cpu usage statistics	Clifford Wolf	2014-08-01	4	-12/+86
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	9	-30/+170
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