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* Merge branch 'xaig' into xc7muxEddie Hung2019-06-194-21/+9
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| * Remove iterator based Module::remove as per @cliffordwolfEddie Hung2019-06-183-18/+9
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| * Remove unncessary headerEddie Hung2019-06-181-3/+0
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| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-183-3/+15
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* | \ Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-183-3/+15
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| * | Merge pull request #1086 from udif/pr_elab_sys_tasks2Clifford Wolf2019-06-182-3/+13
| |\ \ | | | | | | | | Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
| | * | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
| | | | | | | | | | | | | | | | (within always/initial blocks)
| * | | Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-29/+27
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| * | | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
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| * | | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
| | | | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-182-37/+37
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| * | | Clean upEddie Hung2019-06-181-6/+4
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| * | | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-9/+8
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| * | | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-172-33/+59
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| * | | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
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| * | | Simplify commentEddie Hung2019-06-171-1/+1
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-5/+5
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| * | | Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-1/+1
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| * | | &scorr before &sweep, remove &retime as recommendedEddie Hung2019-06-171-1/+1
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-3/+4
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| * | | Copy not move parameters/attributesEddie Hung2019-06-171-3/+4
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-173-27/+37
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| * | | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-173-27/+37
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-1/+1
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| * | | Try -W 300Eddie Hung2019-06-171-1/+2
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| * | | Re-enable &dc2Eddie Hung2019-06-171-1/+1
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* | | | Try -W 300Eddie Hung2019-06-161-1/+2
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-163-299/+33
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| * | | CleanupEddie Hung2019-06-163-299/+33
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-151-2/+2
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| * | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-141-1/+3
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| * | | Leave breadcrumb behindEddie Hung2019-06-141-0/+2
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| * | | Remove redundant conditionEddie Hung2019-06-141-1/+1
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| * | | Revert "Cleanup/optimise toposort in write_xaiger"Eddie Hung2019-06-141-44/+40
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1948e7c846ea318d003148974945d917701a4452. Restores old toposort with optimisations
* | | | Revert "Cleanup/optimise toposort in write_xaiger"Eddie Hung2019-06-141-44/+40
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1948e7c846ea318d003148974945d917701a4452. Restores old toposort with optimisations
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-142-11/+16
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| * | | Update commentEddie Hung2019-06-141-1/+2
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| * | | Check that whiteboxes are synthesisableEddie Hung2019-06-141-4/+8
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| * | | Get rid of compiler warningsEddie Hung2019-06-142-7/+7
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* | | | Update CHANGELOGEddie Hung2019-06-141-2/+3
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* | | | Revert "Remove wide mux inference"Eddie Hung2019-06-145-3/+195
| | | | | | | | | | | | | | | | This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
* | | | Merge branch 'xaig' into xc7muxEddie Hung2019-06-1437-1745/+867
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| * | | As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
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| * | | Cover __APPLE__ too for little to big endianEddie Hung2019-06-142-8/+16
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| * | | Update abc9 -D docEddie Hung2019-06-141-1/+2
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