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| * | | | Module name scope supportZachary Snow2020-08-202-0/+23
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* | | | Merge pull request #2365 from zachjs/const-arg-loop-split-typeclairexen2020-09-012-3/+24
|\ \ \ \ | | | | | | | | | | Fix constant args used with function ports split across declarations
| * | | | Fix constant args used with function ports split across declarationsZachary Snow2020-08-292-3/+24
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* | / / Bump versionYosys Bot2020-09-011-1/+1
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* | | Reorder to prevent crashMiodrag Milanovic2020-08-311-3/+3
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* | | Merge pull request #2368 from YosysHQ/verific_portrangeclairexen2020-08-311-11/+20
|\ \ \ | | | | | | | | Fix import of VHDL enums
| * | | ast recognize lower case x and z and verific gives upper caseMiodrag Milanovic2020-08-301-2/+6
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| * | | Do not check for 1 and 0 onlyMiodrag Milanovic2020-08-301-6/+0
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| * | | Fix import of VHDL enumsMiodrag Milanovic2020-08-301-11/+22
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* | | Bump versionYosys Bot2020-08-301-1/+1
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* | | write_smt2: fix SMT-LIB tutorial URLwhitequark2020-08-291-1/+1
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* | | Bump versionYosys Bot2020-08-291-1/+1
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* | | intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
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* | | Bump versionYosys Bot2020-08-281-1/+1
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* | | Merge pull request #2364 from whitequark/manual-typoMiodrag Milanović2020-08-271-1/+1
|\ \ \ | | | | | | | | manual: fix typo
| * | | manual: fix typo.whitequark2020-08-271-1/+1
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* | | Merge pull request #2357 from whitequark/cxxflags-MPwhitequark2020-08-271-1/+1
|\ \ \ | | | | | | | | Add -MP to CXXFLAGS
| * | | Add -MP to CXXFLAGS.whitequark2020-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | This avoids an issue where deleting or moving headers breaks the next incremental build until the outdated *.d files are deleted.
* | | | Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-273-9/+17
|\ \ \ \ | | | | | | | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-263-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | | | | Merge pull request #2358 from whitequark/rename-ilang-to-rtlilwhitequark2020-08-2728-178/+206
|\ \ \ \ \ | | | | | | | | | | | | Replace "ILANG" with "RTLIL" everywhere
| * | | | | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-2628-178/+206
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* | | | | dfflegalize: Fix decision tree for adffe.Marcelina Kościelnicka2020-08-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an adffe is being legalized, and is not natively supported, prioritize unmapping to adff over converting to dffsre if dffsre is not natively supported itself. Fixes #2361.
* | | | | Bump versionYosys Bot2020-08-271-1/+1
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* | | | | intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-267-16/+147
|/ / / / | | | | | | | | | | | | | | | | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* | | | Merge pull request #2355 from YosysHQ/verific_improvementsMiodrag Milanović2020-08-261-1/+223
|\ \ \ \ | |/ / / |/| | | Add formal apps and template generators
| * | | Add formal apps and template generatorsMiodrag Milanovic2020-08-261-1/+223
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* | | | Merge pull request #2351 from pbsds/proc_nomuxwhitequark2020-08-261-1/+10
|\ \ \ \ | |/ / / |/| | | Add -nomux switch to proc
| * | | proc: Add -nomux switchPeder Bergebakken Sundt2020-08-201-1/+10
| | | | | | | | | | | | | | | | running proc -nomux will ommit the proc_mux pass
* | | | Bump versionYosys Bot2020-08-231-1/+1
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* | | | Merge pull request #2349 from nmoroze/smt2-bugfixclairexen2020-08-221-9/+20
|\ \ \ \ | | | | | | | | | | Ensure smt2 comments are associated with accessors
| * | | | Ensure smt2 comments are associated with accessorsNoah Moroze2020-08-201-9/+20
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* | | | | Bump versionYosys Bot2020-08-211-1/+1
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* | | | synth_intel: Remove incomplete Arria 10 GX support.Marcelina Kościelnicka2020-08-215-192/+4
| |/ / |/| | | | | | | | | | | | | | The techmap rules for this target do not work in the first place (note lack of >2-input LUT mappings), and if proper support is ever added, it'd be better placed in the synth_intel_alm backend.
* | | intel: move Cyclone V support to intel_almDan Ravensloft2020-08-207-203/+11
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* | | Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixesclairexen2020-08-203-81/+38
|\ \ \ | | | | | | | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.
| * | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-203-81/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* | | | Merge pull request #2344 from YosysHQ/mwk/opt_share-fixesclairexen2020-08-204-223/+192
|\ \ \ \ | | | | | | | | | | opt_share: Refactor, fix some bugs.
| * | | | opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-174-223/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* | | | | Merge pull request #2337 from YosysHQ/mwk/clean-keep-wireclairexen2020-08-201-4/+9
|\ \ \ \ \ | | | | | | | | | | | | opt_clean: Fix module keep rules.
| * | | | | opt_clean: Fix module keep rules.Marcelina Kościelnicka2020-08-091-4/+9
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | - wires with keep attribute now force a module to be kept - presence of $memwr and $meminit cells no longer forces a module to be kept
* | | | | Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signedclairexen2020-08-202-5/+12
|\ \ \ \ \ | | | | | | | | | | | | peeopt.shiftmul: Add a signedness check.
| * | | | | peeopt.shiftmul: Add a signedness check.Marcelina Kościelnicka2020-08-052-5/+12
| | |_|_|/ | |/| | | | | | | | | | | | | Fixes #2332.
* | | | | Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-2011-1661/+129
|\ \ \ \ \ | | | | | | | | | | | | Remove passes redundant with opt_dff
| * | | | | Remove now-redundant dff2dffe pass.Marcelina Kościelnicka2020-08-072-415/+0
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| * | | | | Remove now-redundant dff2dffs pass.Marcelina Kościelnicka2020-08-073-216/+0
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| * | | | | peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-075-318/+129
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| * | | | | Remove now-redundant opt_rmdff pass.Marcelina Kościelnicka2020-08-072-712/+0
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* | | | | Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fixclairexen2020-08-202-1/+37
|\ \ \ \ \ | | | | | | | | | | | | techmap.CONSTMAP: Handle outputs before inputs.
| * | | | | techmap.CONSTMAP: Handle outputs before inputs.Marcelina Kościelnicka2020-08-052-1/+37
| | |/ / / | |/| | | | | | | | | | | | | Fixes #2321.
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