| Commit message (Collapse) | Author | Age | Files | Lines |
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Fix constant args used with function ports split across declarations
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Fix import of VHDL enums
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manual: fix typo
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Add -MP to CXXFLAGS
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This avoids an issue where deleting or moving headers breaks the next
incremental build until the outdated *.d files are deleted.
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flatten, techmap: don't canonicalize tpl driven bits via sigmap
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For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:
module foo(inout a, b);
assign a = b;
endmodule
module bar(output c);
foo f(c, 1'b0);
endmodule
Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).
This issue was introduced in 9f772eb9.
Fixes #2183.
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Replace "ILANG" with "RTLIL" everywhere
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The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
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When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.
Fixes #2361.
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Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
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Add formal apps and template generators
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Add -nomux switch to proc
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running proc -nomux will ommit the proc_mux pass
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Ensure smt2 comments are associated with accessors
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The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
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techmap/shift_shiftx: Remove the "shiftx2mux" special path.
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Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering. This path was needlessly
overcomplicated and contained bugs.
Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling). This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.
Fixes #2346.
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opt_share: Refactor, fix some bugs.
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Fixes #2334.
Fixes #2335.
Fixes #2336.
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opt_clean: Fix module keep rules.
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- wires with keep attribute now force a module to be kept
- presence of $memwr and $meminit cells no longer forces a module to be
kept
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peeopt.shiftmul: Add a signedness check.
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Fixes #2332.
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Remove passes redundant with opt_dff
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techmap.CONSTMAP: Handle outputs before inputs.
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Fixes #2321.
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