| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Add author name | Eddie Hung | 2019-03-19 | 1 | -0/+1 |
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| * | Add aiger tests to make tests | Eddie Hung | 2019-02-19 | 1 | -0/+1 |
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| * | Merge branch 'master' into read_aiger | Eddie Hung | 2019-02-19 | 0 | -0/+0 |
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| | * | Merge pull request #805 from eddiehung/dff_init | Eddie Hung | 2019-02-19 | 4 | -2/+76 |
| | |\ | | | | | | | write_verilog to write initial statement for initial flop state | ||||
| * | | | Fix for using POSIX basename | Eddie Hung | 2019-02-19 | 1 | -2/+4 |
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| * | | | Missing OSX headers? | Eddie Hung | 2019-02-17 | 1 | -0/+5 |
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| * | | | Revert "Missing headers for Xcode?" | Eddie Hung | 2019-02-17 | 1 | -2/+0 |
| | | | | | | | | | | | | | This reverts commit c23e3f07517d4818d9ab1b532250353492cf50c2. | ||||
| * | | | Merge branch 'dff_init' into read_aiger | Eddie Hung | 2019-02-17 | 3 | -104/+56 |
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| | * | | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 |
| | | | | | | | | | | | | | per @cliffordwolf | ||||
| | * | | Revert "Add INIT parameter to all ff/latch cells" | Eddie Hung | 2019-02-17 | 2 | -86/+43 |
| | | | | | | | | | | | | | This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8. | ||||
| * | | | read_aiger to ignore line after ands for ascii, not binary | Eddie Hung | 2019-02-17 | 1 | -2/+1 |
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| * | | | One more merge conflict | Eddie Hung | 2019-02-17 | 1 | -6/+1 |
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| * | | | Merge branch 'dff_init' into read_aiger | Eddie Hung | 2019-02-17 | 0 | -0/+0 |
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| | * | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 9 | -100/+345 |
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| * | | | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-02-17 | 9 | -100/+349 |
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| | * | | Merge pull request #811 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-17 | 6 | -56/+298 |
| | |\ \ | | | | | | | | | Update cells supported for verilog to FIRRTL conversion. | ||||
| | | * | | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 |
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| | | * | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 |
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| | | * | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 5 | -55/+317 |
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | ||||
| | * | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 |
| | |\ \ | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports | ||||
| | | * | | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760. | ||||
| | * | | | Merge pull request #806 from daveshah1/fsm_opt_no_reset | Clifford Wolf | 2019-02-12 | 1 | -1/+2 |
| | |\ \ \ | | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state | ||||
| | | * | | | fsm_opt: Fix runtime error for FSMs without a reset state | David Shah | 2019-02-07 | 1 | -1/+2 |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Missing headers for Xcode? | Eddie Hung | 2019-02-12 | 1 | -0/+2 |
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| * | | | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 |
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| | * | | | | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
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| | * | | | | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 |
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| | * | | | | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
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| * | | | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 |
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| * | | | | Merge remote-tracking branch 'origin/dff_init' into read_aiger | Eddie Hung | 2019-02-08 | 2 | -7/+7 |
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| | * | | | Cope WIDTH of ff/latch cells is default of zero | Eddie Hung | 2019-02-06 | 1 | -6/+6 |
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| | * | | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 |
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| * | | | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 |
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| * | | | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 |
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| * | | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 |
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| * | | | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 |
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| * | | | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 |
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| * | | | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 |
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| * | | | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 |
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| * | | | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 |
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| * | | | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 |
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| * | | | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 |
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| * | | | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 |
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| * | | | | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 |
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| * | | | | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 |
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| * | | | | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 |
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index : iCE40/yosys | |
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