| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | Renamed GP4_V* cells to GP_V* for consistency | Andrew Zonenberg | 2016-03-26 | 1 | -2/+3 |
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| * | Merge pull request #136 from ravenexp/master | Clifford Wolf | 2016-03-25 | 2 | -17/+20 |
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| | * | Optionally use ${CC} when compiling test utils. | Sergey Kvachonok | 2016-03-25 | 1 | -1/+1 |
| | * | Allow redefining pkg-config Makefile command. | Sergey Kvachonok | 2016-03-25 | 1 | -2/+4 |
| | * | Allow redefining binary and data install locations. | Sergey Kvachonok | 2016-03-25 | 1 | -14/+15 |
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| * | Do not set "nosync" on task outputs, fixes #134 | Clifford Wolf | 2016-03-24 | 1 | -1/+2 |
| * | Fixed handling of inverters (aka 1-input luts) in nlutmap | Clifford Wolf | 2016-03-23 | 1 | -2/+2 |
| * | Added GP_DFFS, GP_DFFR, and GP_DFFSR | Clifford Wolf | 2016-03-23 | 4 | -21/+76 |
| * | Added GP_DFF INIT parameter | Clifford Wolf | 2016-03-23 | 2 | -0/+4 |
| * | Added ast.h to exported headers | Clifford Wolf | 2016-03-22 | 1 | -0/+1 |
| * | Cleanup abstract modules at end of "hierarchy -top" | Clifford Wolf | 2016-03-21 | 1 | -2/+0 |
| * | Support for abstract modules in chparam | Clifford Wolf | 2016-03-21 | 1 | -0/+6 |
| * | Added support for $stop system task | Clifford Wolf | 2016-03-21 | 1 | -5/+5 |
| * | Improvements in synth_greenpak4, added -part option | Clifford Wolf | 2016-03-21 | 1 | -30/+25 |
| * | Improvements in ABCEXTERNAL handling | Clifford Wolf | 2016-03-19 | 3 | -11/+18 |
| * | Merge pull request #130 from ravenexp/master | Clifford Wolf | 2016-03-19 | 2 | -4/+16 |
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| | * | Support calling out to an external ABC. | Sergey Kvachonok | 2016-03-19 | 2 | -4/+16 |
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| * | Added $display %m support, fixed mem leak in $display, fixes #128 | Clifford Wolf | 2016-03-19 | 1 | -20/+44 |
| * | Added black box modules for all the 7-series design elements (as listed in ug... | Clifford Wolf | 2016-03-19 | 4 | -0/+3441 |
| * | Fixed localparam signdness, fixes #127 | Clifford Wolf | 2016-03-18 | 1 | -1/+1 |
| * | Set "nosync" attribute on internal task/function wires | Clifford Wolf | 2016-03-18 | 1 | -0/+1 |
| * | Fixed Verilog parser fix and more similar improvements | Clifford Wolf | 2016-03-15 | 1 | -18/+9 |
| * | Use left-recursive rule for cell_port_list in Verilog parser. | Andrew Becker | 2016-03-15 | 1 | -6/+10 |
| * | Bugfix in write_verilog for RTLIL processes | Clifford Wolf | 2016-03-14 | 1 | -9/+20 |
| * | Cleanups and improvements in examples/cmos/ | Clifford Wolf | 2016-03-11 | 5 | -12/+19 |
| * | Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956' | Clifford Wolf | 2016-03-11 | 5 | -9/+76 |
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| | * | Completed ngspice digital example with verilog tb | Uros Platise | 2016-03-05 | 5 | -9/+76 |
| * | | Fixed typos in verilog_defaults help message | Clifford Wolf | 2016-03-10 | 1 | -3/+3 |
| * | | Added "write_edif -nogndvcc" | Clifford Wolf | 2016-03-08 | 1 | -17/+34 |
| * | | Added examples/cxx-api/evaldemo.cc | Clifford Wolf | 2016-03-08 | 1 | -0/+55 |
| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-03-07 | 7 | -25/+123 |
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| | * | Added digital (xspice) example code to examples/cmos/ | Clifford Wolf | 2016-03-02 | 4 | -1/+70 |
| | * | Be more conservative with net names in spice output | Clifford Wolf | 2016-03-02 | 1 | -18/+47 |
| | * | Merge pull request #119 from SebKuzminsky/spelling-fixes | Clifford Wolf | 2016-02-29 | 2 | -6/+6 |
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| | | * | user-facing spelling fixes | Sebastian Kuzminsky | 2016-02-28 | 2 | -6/+6 |
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| * / | Using "mfs" and "lutpack" in ABC lut mapping | Clifford Wolf | 2016-03-07 | 1 | -5/+14 |
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| * | We are now in 0.6+ development | Clifford Wolf | 2016-02-26 | 1 | -1/+1 |
| * | Yosys 0.6 | Clifford Wolf | 2016-02-26 | 1 | -1/+1 |
| * | Fixed BLIF parser for empty port assignments | Clifford Wolf | 2016-02-24 | 1 | -2/+2 |
| * | Use easyer-to-read unoptimized ceil_log2() | Clifford Wolf | 2016-02-15 | 1 | -18/+5 |
| * | Updated ABC to ae7d65e71adc | Clifford Wolf | 2016-02-15 | 1 | -1/+1 |
| * | Updated command reference in manual | Clifford Wolf | 2016-02-14 | 3 | -16/+364 |
| * | Changelog for upcoming 0.6 release | Clifford Wolf | 2016-02-14 | 1 | -0/+88 |
| * | Fixed more visual studio warnings | Clifford Wolf | 2016-02-14 | 1 | -5/+3 |
| * | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 8 | -10/+10 |
| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-02-13 | 1 | -1/+1 |
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| | * | Fixed MXE ABC build | Clifford Wolf | 2016-02-13 | 1 | -1/+1 |
| * | | Added "int ceil_log2(int)" function | Clifford Wolf | 2016-02-13 | 5 | -10/+58 |
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| * | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 |
| * | Support for more Verific primitives (patch I got per email) | Clifford Wolf | 2016-02-13 | 1 | -1/+31 |
