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| * | | | abc9: add flow3mfs scriptLofty2022-02-101-1/+7
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* | | | | Merge pull request #3246 from YosysHQ/gatecat/timing-derive-fixLofty2022-03-281-5/+10
|\ \ \ \ \ | | | | | | | | | | | | abc9_ops: Also derive blackboxes with timing info
| * | | | | abc9_ops: Also derive blackboxes with timing infogatecat2022-03-241-5/+10
| | |/ / / | |/| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | | gowin: Add oscillator primitivesTim Pambor2022-03-281-0/+34
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* | | | Update URL to zlibMiodrag Milanović2022-03-281-1/+1
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* | | | Bump versiongithub-actions[bot]2022-03-261-1/+1
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* | | | Add some more reserve calls to RTLIL::ConstNotAFile2022-03-251-0/+5
| | | | | | | | | | | | | | | | This results in a slight ~0.22% total speedup synthesizing vexriscv
* | | | Merge pull request #3249 from YosysHQ/micko/no_startoffsetMiodrag Milanović2022-03-251-8/+17
|\ \ \ \ | |_|_|/ |/| | | Add -no-startoffset option to write_aiger
| * | | Add -no-startoffset option to write_aigerMiodrag Milanovic2022-03-251-8/+17
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* | | Bump versiongithub-actions[bot]2022-03-251-1/+1
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* | | Merge pull request #3243 from nakengelhardt/fix_aiw_commentMiodrag Milanović2022-03-241-1/+1
|\ \ \ | |/ / |/| | smtbmc: ignore # comment lines
| * | ignore # comment linesN. Engelhardt2022-03-241-1/+1
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* | Bump versiongithub-actions[bot]2022-03-231-1/+1
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* | Update abc with latest fixMiodrag Milanovic2022-03-221-1/+1
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* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* | Bump versiongithub-actions[bot]2022-03-221-1/+1
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* | xilinx: Add RAMB4* blackboxesMarcelina Kościelnicka2022-03-212-1/+695
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* | Bump versiongithub-actions[bot]2022-03-191-1/+1
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* | More verbose warningsMiodrag Milanovic2022-03-182-6/+9
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* | Merge pull request #3236 from YosysHQ/micko/tb_initialMiodrag Milanović2022-03-173-6/+34
|\ \ | | | | | | Recognize registers and set initial state for them in tb
| * | Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-163-6/+34
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* | | Bump versiongithub-actions[bot]2022-03-171-1/+1
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* | Update sim help message.Miodrag Milanovic2022-03-161-1/+2
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* | Bump versiongithub-actions[bot]2022-03-151-1/+1
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* | gowin: add support for Double Data Rate primitivesYRabbit2022-03-141-0/+25
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #3232 from YosysHQ/micko/fst2tbMiodrag Milanović2022-03-141-0/+319
|\ \ | | | | | | Added fst2tb pass for generating testbench
| * | Added fst2tb pass for generating testbenchMiodrag Milanovic2022-03-141-0/+319
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* | | Merge pull request #3213 from antonblanchard/abc-typoClaire Xen2022-03-141-2/+2
|\ \ \ | |/ / |/| | abc: Fix {I} and {P} substitution
| * | abc: Fix {I} and {P} substitutionAnton Blanchard2022-02-231-2/+2
| | | | | | | | | | | | We were searching for {D} after the first match of {I} or {P}.
* | | Proper example codeMiodrag Milanovic2022-03-142-1/+3
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* | | Bump versiongithub-actions[bot]2022-03-121-1/+1
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* | | Merge pull request #3229 from YosysHQ/micko/sim_dateMiodrag Milanović2022-03-111-7/+20
|\ \ \ | | | | | | | | Add date parameter to enable full date/time and version info
| * | | Add date parameter to enable full date/time and version infoMiodrag Milanovic2022-03-111-7/+20
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* | | | Merge pull request #3222 from zachjs/prune-linux-ciMiodrag Milanović2022-03-111-2/+6
|\ \ \ \ | | | | | | | | | | Prune Linux CI builds
| * | | | Prune Linux CI buildsZachary Snow2022-03-111-2/+6
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* | | | | Merge pull request #3228 from YosysHQ/micko/disable_testsMiodrag Milanović2022-03-112-28/+2
|\ \ \ \ \ | | | | | | | | | | | | Disable tests on most of platforms
| * | | | | Disable tests on most of platformsMiodrag Milanovic2022-03-102-28/+2
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* | | | | | Add "sim -q" optionClaire Xenia Wolf2022-03-111-8/+19
| |_|/ / / |/| | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | | Small fix in "sim" help messageClaire Xenia Wolf2022-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | | Merge pull request #3226 from YosysHQ/micko/btor2witnessMiodrag Milanović2022-03-112-10/+171
|\ \ \ \ \ | |_|/ / / |/| | | | Sim support for btor2 witness files
| * | | | FstData already do conversion to VCDMiodrag Milanovic2022-03-111-1/+2
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| * | | | Support cell name in btor witness fileMiodrag Milanovic2022-03-111-5/+14
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| * | | | Fix handling of some formal cells in btor back-endClaire Xenia Wolf2022-03-111-6/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * | | | handle state names of $anyconst and $anyseqMiodrag Milanovic2022-03-111-1/+5
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| * | | | Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
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| * | | | Start work on memory initMiodrag Milanovic2022-03-091-9/+34
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| * | | | Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
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| * | | | cleanupMiodrag Milanovic2022-03-071-1/+2
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| * | | | Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
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