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* Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #996 from mdaiter/ceil_log2_optsClifford Wolf2019-05-072-3/+5
|\ | | | | Optimize ceil_log2 function
| * Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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* | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | More opt_clean cleanupsClifford Wolf2019-05-071-26/+36
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-0619-51/+810
|\ | | | | Add specify parser
| * Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "real" keyword to ilang formatClifford Wolf2019-05-063-2/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-063-12/+32
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| * | Improve write_verilog specify supportClifford Wolf2019-05-043-16/+75
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Update READMEClifford Wolf2019-05-041-5/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | More testingEddie Hung2019-05-032-2/+5
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| * | Fix spacingEddie Hung2019-05-031-6/+6
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| * | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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| * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-0340-405/+931
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| * | | Add specify support to READMEClifford Wolf2019-04-231-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve $specrule interfaceClifford Wolf2019-04-234-13/+23
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve $specrule interfaceClifford Wolf2019-04-233-24/+24
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-239-6/+133
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Preserve $specify[23] cellsClifford Wolf2019-04-231-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-234-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-232-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add specify parserClifford Wolf2019-04-235-33/+253
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-063-13/+66
|\ \ \ \ | | | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| * \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-0635-290/+787
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| * | | | | Further improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-21/+29
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Silently resolve completely unused cell-vs-const driver-driver conflictsClifford Wolf2019-05-011-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-064-44/+181
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | Improve verific -chparam and add hierarchy -chparam
| * | | | | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1
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| * | | | | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
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| * | | | | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
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| * | | | | WIP -chparam support for hierarchy when verificEddie Hung2019-05-033-19/+41
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| * | | | | verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
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* | | | | | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Bugfix in peepopt_shiftmul.pmgClifford Wolf2019-05-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #992 from bwidawsk/bison-fixClifford Wolf2019-05-061-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | verilog_parser: Fix Bison warning
| * | | | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | | | | Merge pull request #989 from YosysHQ/dave/abc_name_improveClifford Wolf2019-05-061-8/+21
|\ \ \ \ \ \ | | | | | | | | | | | | | | ABC name recovery fixes
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