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* intel: Use dfflegalize.Marcelina Kościelnicka2020-07-138-178/+17
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* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-138-128/+38
| | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commitwhitequark2020-07-132-0/+20
|\ | | | | cxxrtl: expose eval() and commit() via the C API
| * cxxrtl: expose eval() and commit() via the C API.whitequark2020-07-122-0/+20
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* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-122-2/+43
| | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* proc_dlatch: Remove init values for combinatorial processes.Marcelina Kościelnicka2020-07-121-0/+33
| | | | Fixes #2258.
* dfflegalize: Gather init values from all wires.Marcelina Kościelnicka2020-07-121-1/+1
| | | | Skipping non-selected wires is unsound in an obvious way.
* Merge pull request #2256 from YosysHQ/claire/fix2241clairexen2020-07-101-0/+2
|\ | | | | Add AST_EDGE support to AstNode::detect_latch()
| * Add AST_EDGE support to AstNode::detect_latch(), fixes #2241Claire Wolf2020-07-101-0/+2
|/ | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2255 from whitequark/bison-Werror-conflictswhitequark2020-07-096-69/+11
|\ | | | | verilog_parser: turn S/R and R/R conflicts into hard errors
| * verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
| | | | | | | | Fixes #2253.
| * Revert PRs #2203 and #2244.whitequark2020-07-095-68/+10
| | | | | | | | | | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* | Merge pull request #2254 from whitequark/cxxrtl-extern-cwhitequark2020-07-091-0/+1
|\ \ | | | | | | cxxrtl: add missing extern "C"
| * | cxxrtl: add missing extern "C".whitequark2020-07-091-0/+1
| |/ | | | | | | This bug was hidden if a header was generated.
* / sf2: Use dfflegalize.Marcelina Kościelnicka2020-07-092-44/+13
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* xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
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* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-095-212/+214
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* Fix issue #2251 (#2252)Lucas Castro2020-07-091-1/+1
| | | | * Fix #2251 - YosysJS ReferenceError: _memset is not defined. Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.
* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-092-17/+118
| | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* Merge pull request #2244 from antmicro/logicclairexen2020-07-094-7/+31
|\ | | | | Add logic type support to parameters
| * Add logic param and integer bad syntax testsKamil Rakoczy2020-07-063-0/+21
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * Support logic typed parametersLukasz Dalek2020-07-061-7/+10
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-098-88/+82
| | | | | | | | | | | | | | This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* | dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-092-0/+71
| | | | | | | | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* | Merge pull request #2246 from YosysHQ/mwk/dfflegalize-typowhitequark2020-07-071-1/+1
|\ \ | | | | | | dfflegalize: typo fix
| * | dfflegalize: typo fixMarcelina Kościelnicka2020-07-071-1/+1
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* | efinix: Use dfflegalize.Marcelina Kościelnicka2020-07-062-15/+53
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* | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-064-158/+49
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* intel_alm: direct M10K instantiationDan Ravensloft2020-07-058-38/+128
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* Naming fixes.Marcelina Kościelnicka2020-07-052-2/+2
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* synth_gowin: ABC9 supportDan Ravensloft2020-07-053-35/+345
| | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
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* Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40Marcelina Kościelnicka2020-07-054-208/+24
|\ | | | | ice40: Use dfflegalize.
| * ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
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* | ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-054-254/+96
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* | Merge pull request #2227 from Ravenslofty/ccachewhitequark2020-07-051-0/+5
|\ \ | | | | | | Add option to use ccache when building
| * | Add option to use ccache when buildingDan Ravensloft2020-07-041-0/+5
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* | | Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
|\ \ \ | | | | | | | | gowin: Fix INIT values in sim library.
| * | | gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
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* | | | dfflegalize: Prefer mapping dff to sdff before adffMarcelina Kościelnicka2020-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This ensures that, when both sync and async FFs are available and abc9 is involved, the sync FFs will be used, and will thus remain available for sequential synthesis.
* | | | opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.Marcelina Kościelnicka2020-07-052-0/+24
| | | | | | | | | | | | | | | | Fixes #2221.
* | | | intel_alm: DSP inferenceDan Ravensloft2020-07-057-9/+209
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* | | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
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* | | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-043-122/+10
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-042-6/+6
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* | tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
| | | | | | | | | | Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
* | abc9: only techmap (* abc9_flop *) modulesEddie Hung2020-07-041-1/+1
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* | intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
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* | abc9: techmap from user design to allow abc9_flop modules to be composedEddie Hung2020-07-041-1/+1
| | | | | | | | from other primitives
* | intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
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