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* pmux2shift: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-15/+4
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* wreduce: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-37/+7
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* techmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+4
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* shregmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-39/+10
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* abc: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-25/+6
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* dffinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+7
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* zinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-242-45/+13
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* dfflegalize: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-80/+25
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* clk2fflogic: Support all FF types.Marcelina Kościelnicka2020-07-2420-324/+245
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* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-244-6/+88
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* Add utility module for representing flip-flops.Marcelina Kościelnicka2020-07-232-0/+441
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* memory_dff: recognize more dff cellsMarcelina Kościelnicka2020-07-231-11/+112
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* Add utility module for dealing with init attributes.Marcelina Kościelnicka2020-07-232-0/+147
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* Merge pull request #2285 from YosysHQ/mwk/techmap-cellnameclairexen2020-07-234-1/+50
|\ | | | | techmap: Add _TECHMAP_CELLNAME_ special parameter.
| * techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-214-1/+50
| | | | | | | | | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* | Merge pull request #2294 from Ravenslofty/intel_alm_timingsclairexen2020-07-235-78/+95
|\ \ | | | | | | intel_alm: add additional ABC9 timings
| * | intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-235-78/+95
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* | | Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-233-150/+2
| |/ |/| | | | | | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #2215 from boqwxp/qbfsat-solver-optionsclairexen2020-07-214-4/+45
|\ \ | | | | | | qbfsat, smt2, smtio: Add `-solver-option` to allow specifying SMT-LIBv2 `(set-option ...)` commands
| * | smtio: Emit `mode: start` options before `set-logic` command and any other ↵Alberto Gonzalez2020-07-201-1/+8
| | | | | | | | | | | | | | | | | | options after it. Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode.
| * | smtio: Add support for parsing `yosys-smt2-solver-option` info statements.Alberto Gonzalez2020-07-201-3/+10
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| * | qbfsat: Add `-solver-option` option.Alberto Gonzalez2020-07-202-1/+15
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| * | smt2: Add `-solver-option` option.Alberto Gonzalez2020-07-201-0/+13
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* | Merge pull request #2282 from YosysHQ/claire/satunsatclairexen2020-07-202-4/+4
|\ \ | | | | | | Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
| * | Only allow "sat" and "unsat" smt solver responses in yosys-smtbmcClaire Wolf2020-07-202-4/+4
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | celltypes: Fix EN port name for some FF types.Marcelina Kościelnicka2020-07-201-4/+4
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* | Merge pull request #2276 from YosysHQ/mwk/satgen-ccclairexen2020-07-203-1166/+1190
|\ \ | |/ |/| satgen: Move importCell out of the header.
| * satgen: Move importCell out of the header.Marcelina Kościelnicka2020-07-193-1166/+1190
|/ | | | | This function has no hope of ever getting inlined anyway, and it speeds up yosys compile time by 7%.
* Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fixMiodrag Milanović2020-07-171-2/+6
|\ | | | | sf2: Emit CLKINT even if -clkbuf not passed
| * sf2: Emit CLKINT even if -clkbuf not passedMarcelina Kościelnicka2020-07-171-2/+6
|/ | | | This restores pre #2229 behavior.
* Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fixMiodrag Milanović2020-07-171-12/+12
|\ | | | | anlogic: Fix FF mapping.
| * anlogic: Fix FF mapping.Marcelina Kościelnicka2020-07-171-12/+12
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* | Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobsclairexen2020-07-164-214/+135
|\ \ | | | | | | sf2: replace sf2_iobs with {clkbuf,iopad}map
| * | sf2: replace sf2_iobs with {clkbuf,iopad}mapDan Ravensloft2020-07-094-214/+135
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* | | Merge pull request #2273 from whitequark/write-verilog-always-star-initialclairexen2020-07-161-0/+5
|\ \ \ | |_|/ |/| | verilog_backend: in non-SV mode, add a trigger for `always @*`
| * | verilog_backend: in non-SV mode, add a trigger for `always @*`.whitequark2020-07-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit only affects translation of RTLIL processes (for which there is limited support). Due to the event-driven nature of Verilog, processes like reg x; always @* x <= 1; may never execute. This can be fixed in SystemVerilog code by using `always_comb` instead of `always @*`, but in Verilog-2001 the options are limited. This commit implements the following workaround: reg init = 0; reg x; always @* begin if (init) begin end x <= 1; end Fixes #2271.
* | | Merge pull request #2272 from whitequark/write-verilog-svclairexen2020-07-162-11/+20
|\| | | | | | | | verilog_backend: add `-sv` option, make `-o <filename>.sv` work
| * | verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-162-11/+20
| | | | | | | | | | | | See #2271.
* | | Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-164-62/+49
|\ \ \ | | | | | | | | anlogic: Use dfflegalize.
| * | | anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-144-62/+49
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* | | | Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbufMiodrag Milanović2020-07-165-122/+11
|\ \ \ \ | | | | | | | | | | efinix: Nuke efinix_gbuf in favor of clkbufmap.
| * | | | efinix: Nuke efinix_gbuf in favor of clkbufmap.Marcelina Kościelnicka2020-07-045-122/+11
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* | | | | Merge pull request #2270 from whitequark/cxxrtl-fix-typowhitequark2020-07-161-1/+1
|\ \ \ \ \ | | | | | | | | | | | | cxxrtl: fix typo
| * | | | | cxxrtl: fix typo. NFC.whitequark2020-07-141-1/+1
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* | | | | Merge pull request #2269 from YosysHQ/claire/bisonwallwhitequark2020-07-152-64/+57
|\ \ \ \ \ | | | | | | | | | | | | Use "bison -Wall -Werror" for verilog front-end
| * | | | | Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | | Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | | Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | | Run bison with -Wall for verilog front-endClaire Wolf2020-07-151-1/+1
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | | Merge pull request #2257 from antmicro/fix-conflictsclairexen2020-07-155-9/+59
|\ \ \ \ \ | | | | | | | | | | | | Restore #2203 and #2244 and fix parser conflicts
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