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* nexus: More efficient CO mappingDavid Shah2020-12-021-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #2460 from pepijndevos/simple-gowinMiodrag Milanović2020-12-011-3/+32
|\ | | | | add -noalu and -json option for apicula
| * add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
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* Bump versionYosys Bot2020-11-261-1/+1
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* Merge pull request #2452 from whitequark/rtlil-remove-dot-identifierswhitequark2020-11-251-1/+0
|\ | | | | rtlil: remove dotted identifiers
| * rtlil: remove dotted identifiers.whitequark2020-11-251-1/+0
| | | | | | | | No one knows where they came from and they never did anything useful.
* | Merge pull request #2453 from YosysHQ/mmicko/verilog_assignmentsMiodrag Milanović2020-11-251-6/+26
|\ \ | | | | | | Generate only simple assignments in verilog backend
| * | Add verilog backend option for simple_lhsMiodrag Milanovic2020-11-251-6/+22
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| * | generate only simple assignments in verilog backendMiodrag Milanovic2020-11-251-5/+9
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* | Merge pull request #2133 from dh73/nodev_headClaire Xen2020-11-2518-65/+322
|\ \ | | | | | | Adding latch tests for shift&mask AST dynamic part-select enhancements
| * | Removing trailing whitespacediego2020-06-101-30/+30
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| * | Adding latch tests for shift&mask AST dynamic part-select enhancementsdiego2020-06-0918-68/+325
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* | | Merge pull request #2442 from cr1901/sccachewhitequark2020-11-251-2/+7
|\ \ \ | | | | | | | | Makefile: Add disabled-by-default ENABLE_SCCACHE config option.
| * | | Makefile: Update ABCREV to bring in sccache fixes.William D. Jones2020-11-241-1/+1
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| * | | Makefile: Add disabled-by-default ENABLE_SCCACHE config option.William D. Jones2020-11-191-1/+6
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* | | Merge pull request #2450 from nitz/sim-vcd-filenamewhitequark2020-11-251-1/+3
|\ \ \ | | | | | | | | Add rewrite_filename for sim -vcd argument.
| * | | Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
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* | | | Bump versionYosys Bot2020-11-251-1/+1
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* | | | Merge pull request #2428 from whitequark/check-processeswhitequark2020-11-241-22/+55
|\ \ \ \ | | | | | | | | | | check: add support for processes
| * | | | check: add support for processes.whitequark2020-11-031-3/+38
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| * | | | check: reformat log/help text to match most other passeswhitequark2020-11-031-19/+17
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* | | | | Merge pull request #2448 from nitz/tcl-script-documentation-fixesMiodrag Milanović2020-11-241-0/+2
|\ \ \ \ \ | | | | | | | | | | | | Tcl script documentation fixes
| * | | | | tcl -h message only if YOSYS_ENABLE_TCL defined.nitz2020-11-231-0/+2
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* | | | | Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parametersMiodrag Milanović2020-11-241-58/+294
|\ \ \ \ \ | |/ / / / |/| | | | Add firrtl backend support for generic parameters in blackbox components
| * | | | Formatting fixesSahand Kashani2020-11-231-10/+7
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| * | | | Add support for real-valued parameters + preserve type of parametersSahand Kashani2020-08-061-38/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for real-valued parameters in blackboxes. Additionally, parameters now retain their types are no longer all encoded as strings. There is a caveat with this implementation due to my limited knowledge of yosys, more specifically to how yosys encodes bitwidths of parameter values. The example below can motivate the implementation choice I took. Suppose a verilog component is declared with the following parameters: parameter signed [26:0] test_signed; parameter [26:0] test_unsigned; parameter signed [40:0] test_signed_large; If you instantiate it as follows: defparam <inst_name> .test_signed = 49; defparam <inst_name> .test_unsigned = 40'd35; defparam <inst_name> .test_signed_large = 40'd12; If you peek in the RTLIL::Const structure corresponding to these params, you realize that parameter "test_signed" is being considered as a 32-bit value since it's declared as "49" without a width specifier, even though the parameter is defined to have a maximum width of 27 bits. A similar issue occurs for parameter "test_unsigned" where it is supposed to take a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above, then yosys considers the value to be 40 bits. I suppose this is due to the type being defined by the RHS rather than the definition. Regardless of this, I emit the same widths as what the user specifies on the RHS when generating firrtl IR.
| * | | | Add firrtl backend support for generic parameters in blackbox componentsSahand Kashani2020-07-231-58/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous blackbox components were just emitted with their interface ports, but their generic parameters were never emitted and it was therefore impossible to customize them. This commit adds support for blackbox generic parameters, though support is only provided for INTEGER and STRING parameters. Other types of parameters such as DOUBLEs, ..., would result in undefined behavior here. This allows the emission of custom extmodule instances such as the following: extmodule fourteennm_lcell_comb_<instName>: input cin: UInt<1> output combout: UInt<1> output cout: UInt<1> input dataa: UInt<1> input datab: UInt<1> input datac: UInt<1> input datad: UInt<1> input datae: UInt<1> input dataf: UInt<1> input datag: UInt<1> input datah: UInt<1> input sharein: UInt<1> output shareout: UInt<1> output sumout: UInt<1> defname = fourteennm_lcell_comb parameter extended_lut = "off" parameter lut_mask = "b0001001000010010000100100001001000010010000100100001001000010010" parameter shared_arith = "off"
* | | | | Bump versionYosys Bot2020-11-211-1/+1
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* | | | | Merge pull request #2443 from YosysHQ/dave/nexus-mult-inferMiodrag Milanović2020-11-204-13/+151
|\ \ \ \ \ | |_|_|/ / |/| | | | nexus: Multiplier inference support
| * | | | nexus: DSP inference supportDavid Shah2020-11-204-13/+151
|/ / / / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Bump versionYosys Bot2020-11-191-1/+1
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* | | | Merge pull request #2441 from YosysHQ/dave/nexus_dsp_simMiodrag Milanović2020-11-183-250/+573
|\ \ \ \ | | | | | | | | | | nexus: Add DSP simulation model
| * | | | nexus: Add DSP simulation modelDavid Shah2020-11-183-250/+573
| | |/ / | |/| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Fix duplicated parameter name typoMiodrag Milanovic2020-11-181-1/+1
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* | | | Bump versionYosys Bot2020-11-171-1/+1
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* | | | backends/blif: Remove unused vector of strings (#2420)William Woodruff2020-11-161-57/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * backends/blif: Remove unused vector of strings For reasons that are unclear to me, this was being used to store every result of `cstr` before returning them. The vector was never accessed otherwise, resulting in a huge unnecessary memory sink when emitting to BLIF. * backends/blif: Remove CSTR macro * backends/blif: Actually call str()
* | | | Merge pull request #2438 from kbeckmann/gowin_rpllMiodrag Milanović2020-11-161-0/+45
|\ \ \ \ | | | | | | | | | | synth_gowin: Add rPLL blackbox
| * | | | synth_gowin: Add rPLL blackboxKonrad Beckmann2020-11-111-0/+45
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* | | | Bump versionYosys Bot2020-11-111-1/+1
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* | | | Merge pull request #2433 from YosysHQ/paths_as_globalsMiodrag Milanović2020-11-104-43/+63
|\ \ \ \ | | | | | | | | | | Expose abc and data paths as globals for pyosys
| * | | | Expose abc and data paths as globalsMiodrag Milanovic2020-11-064-43/+63
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* | | | Bump versionYosys Bot2020-11-081-1/+1
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* | | | Merge pull request #2414 from zeldin/abc-depend-clang-fixwhitequark2020-11-071-0/+4
|\ \ \ \ | | | | | | | | | | Prevent CXXFLAGS from leaking to abc Makefile
| * | | | Prevent CXXFLAGS from leaking to abc MakefileMarcus Comstedt2020-11-071-0/+4
| | | | | | | | | | | | | | | | | | | | This fixes an issue with abc/depends.sh when the compiler is clang.
* | | | | Merge pull request #2432 from Xiretza/nexus-testsMiodrag Milanović2020-11-071-19/+3
|\ \ \ \ \ | |_|/ / / |/| | | | Update nexus arch tests to new harness
| * | | | Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
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* | | | Bump versionYosys Bot2020-11-031-1/+1
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* | | | Merge pull request #2426 from whitequark/cxxrtl-auto-topwhitequark2020-11-021-7/+26
|\ \ \ \ | | | | | | | | | | cxxrtl: run `hierarchy -auto-top` if no top module is present
| * | | | cxxrtl: run `hierarchy -auto-top` if no top module is present.whitequark2020-11-021-7/+26
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In most cases, a CXXRTL simulation would use a top module, either because this module serves as an entry point to the CXXRTL C API, or because the outputs of a top module are unbuffered, improving performance. Taking this into account, the CXXRTL backend now runs `hierarchy -auto-top` if there is no top module. For the few cases where this behavior is unwanted, it now accepts a `-nohierarchy` option. Fixes #2373.
* | | | Bump versionYosys Bot2020-11-021-1/+1
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