| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | | * | | | | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 | |
| | | | |/ / / / / | ||||||
| | | | * | | | | | Merge remote-tracking branch 'origin/dff_init' into read_aiger | Eddie Hung | 2019-02-08 | 2 | -7/+7 | |
| | | | |\ \ \ \ \ | ||||||
| | | | * | | | | | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | * | | | | | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 | |
| | | | * | | | | | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 | |
| | | | * | | | | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 | |
| | | | * | | | | | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | * | | | | | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 | |
| | | | * | | | | | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 | |
| | | | * | | | | | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 | |
| | | | * | | | | | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 | |
| | | | * | | | | | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 | |
| | | | * | | | | | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 | |
| | | | * | | | | | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 | |
| | | | * | | | | | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | * | | | | | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 | |
| | | | * | | | | | | Handle latch symbols too | Eddie Hung | 2019-02-08 | 1 | -3/+1 | |
| | | | * | | | | | | Remove return after log_error | Eddie Hung | 2019-02-08 | 1 | -27/+9 | |
| | | | * | | | | | | Add support for symbol tables | Eddie Hung | 2019-02-08 | 1 | -1/+49 | |
| | | | * | | | | | | Stub for binary AIGER | Eddie Hung | 2019-02-08 | 1 | -3/+8 | |
| | | | * | | | | | | Refactor | Eddie Hung | 2019-02-06 | 1 | -1/+8 | |
| | | | * | | | | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 7 | -50/+172 | |
| | | | |\ \ \ \ \ \ | ||||||
| | | | * | | | | | | | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 | |
| | | | * | | | | | | | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+0 | |
| | | | * | | | | | | | WIP | Eddie Hung | 2019-02-06 | 3 | -0/+247 | |
| | | | * | | | | | | | Add tests | Eddie Hung | 2019-02-04 | 16 | -8/+109 | |
| * | | | | | | | | | | Make output port a non chain user | Eddie Hung | 2019-03-19 | 1 | -2/+4 | |
| * | | | | | | | | | | Fix shregmap to correctly recognise non chain users; cleanup | Eddie Hung | 2019-03-18 | 1 | -17/+15 | |
| * | | | | | | | | | | shiftx NULL pointer check | Eddie Hung | 2019-03-18 | 1 | -8/+10 | |
| * | | | | | | | | | | Cleanup | Eddie Hung | 2019-03-16 | 1 | -35/+25 | |
| * | | | | | | | | | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 2 | -13/+18 | |
| * | | | | | | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 | |
| * | | | | | | | | | | Working | Eddie Hung | 2019-03-15 | 3 | -274/+434 | |
| * | | | | | | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 | |
| * | | | | | | | | | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 | |
| * | | | | | | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 2 | -17/+4 | |
| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 82 | -584/+2483 | |
| |\| | | | | | | | | | ||||||
| | * | | | | | | | | | Merge pull request #868 from YosysHQ/clifford/fixmem | Clifford Wolf | 2019-03-13 | 2 | -40/+24 | |
| | |\ \ \ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | | | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 | |
| | | * | | | | | | | | | Improve handling of memories used in mem index expressions on LHS of an assig... | Clifford Wolf | 2019-03-12 | 1 | -5/+16 | |
| | | * | | | | | | | | | Remove outdated "blocking assignment to memory" warning | Clifford Wolf | 2019-03-12 | 1 | -10/+0 | |
| | | * | | | | | | | | | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 | Clifford Wolf | 2019-03-12 | 1 | -6/+8 | |
| | | |/ / / / / / / / | ||||||
| | * | | | | | | | | | Fix a bug in handling quotes in multi-cmd lines in Yosys scripts | Clifford Wolf | 2019-03-12 | 1 | -1/+7 | |
| | * | | | | | | | | | Merge pull request #866 from YosysHQ/clifford/idstuff | Clifford Wolf | 2019-03-12 | 5 | -5/+71 | |
| | |\ \ \ \ \ \ \ \ \ | | |/ / / / / / / / | |/| | | | | | | | | ||||||
| | | * | | | | | | | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 5 | -5/+71 | |
| | * | | | | | | | | | Merge pull request #864 from YosysHQ/svalabelfix | Eddie Hung | 2019-03-11 | 2 | -92/+66 | |
| | |\ \ \ \ \ \ \ \ \ | | |/ / / / / / / / | |/| | | | | | | | | ||||||
| | | * | | | | | | | | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 2 | -92/+66 | |
| | * | | | | | | | | | Add ENABLE_GLOB Makefile switch | Clifford Wolf | 2019-03-11 | 2 | -3/+10 | |
| | |/ / / / / / / / | ||||||
| | * | | | | | | | | Fix typo in ice40_braminit help msg | Clifford Wolf | 2019-03-09 | 1 | -1/+1 | |
| | * | | | | | | | | Merge pull request #859 from smunaut/ice40_braminit | Clifford Wolf | 2019-03-09 | 4 | -37/+212 | |
| | |\ \ \ \ \ \ \ \ | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |