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* Add log_warning_noprefix() API, Use for Verific warnings and errorsClifford Wolf2017-07-273-1/+37
* Add "verific -import -n" and "verific -import -nosva"Clifford Wolf2017-07-271-14/+36
* Improve SVA tests, add Makefile and scriptsClifford Wolf2017-07-2711-9/+110
* Improve Verific SVA import: negedge and $pastClifford Wolf2017-07-271-6/+49
* Improve Verific SVA importerClifford Wolf2017-07-271-37/+58
* Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ope...Clifford Wolf2017-07-261-0/+47
* Improve Verific bindings (mostly related to SVA)Clifford Wolf2017-07-261-110/+320
* Improve "help verific" messageClifford Wolf2017-07-251-5/+5
* Add "verific -extnets"Clifford Wolf2017-07-251-23/+130
* Add "using std::get" to yosys.hClifford Wolf2017-07-251-0/+1
* Improve "verific -all" handlingClifford Wolf2017-07-251-26/+45
* Add "verific -import -d <dump_file"Clifford Wolf2017-07-241-6/+35
* Add "verific -import -flatten" and "verific -import -v"Clifford Wolf2017-07-241-107/+164
* Add more SVA test cases for future Verific workClifford Wolf2017-07-225-1/+74
* Add "verific -import -k"Clifford Wolf2017-07-221-42/+51
* Add error for cell output ports that are connected to constantsClifford Wolf2017-07-221-20/+21
* Add some simple SVA test cases for future Verific workClifford Wolf2017-07-224-0/+45
* Improve docs for verific bindings, add simply sby exampleClifford Wolf2017-07-225-48/+89
* Fix handling of empty cell port assignments (i.e. ignore them)Clifford Wolf2017-07-212-0/+6
* Fix "read_blif -wideports" handling of cells with wide portsClifford Wolf2017-07-211-3/+33
* Add a paragraph about pre-defined macros to read_verilog help messageClifford Wolf2017-07-211-0/+4
* Add verilator support to testbenches generated by yosys-smtbmcClifford Wolf2017-07-211-3/+15
* Change intptr_t to uintptr_t in hashlib.hClifford Wolf2017-07-181-1/+1
* Merge pull request #363 from rqou/masterClifford Wolf2017-07-182-1/+6
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| * makefile: Add the option to use libtermcapRobert Ou2017-07-171-0/+5
| * Fix build warnings for win64Robert Ou2017-07-171-1/+1
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* Add $alu to list of supported cells for "stat -width"Clifford Wolf2017-07-141-1/+1
* Generate FSM-style testbenches in smtbmcClifford Wolf2017-07-121-5/+23
* Fix the fixed handling of x-bits in EDIF back-endClifford Wolf2017-07-111-1/+0
* Fix handling of x-bits in EDIF back-endClifford Wolf2017-07-111-1/+11
* Add attributes and parameter support to JSON front-endClifford Wolf2017-07-102-7/+52
* Add techlibs/xilinx/lut2lut.vClifford Wolf2017-07-102-0/+66
* Add JSON front-endClifford Wolf2017-07-082-0/+472
* Change s/asserts/assertions/ in yosys-smtbmc log messagesClifford Wolf2017-07-071-2/+2
* Add "yosys-smtbmc --presat"Clifford Wolf2017-07-071-3/+23
* Fix generation of multiple outputs for same AIG node in write_aigerClifford Wolf2017-07-051-13/+30
* Add write_table commandClifford Wolf2017-07-052-0/+123
* Add Verific Release information to logClifford Wolf2017-07-041-0/+12
* Fix some c++ clang compiler errorsClifford Wolf2017-07-031-3/+3
* Apply minor coding style changes to coolrunner2 targetClifford Wolf2017-07-032-1/+1
* Merge pull request #352 from rqou/masterClifford Wolf2017-07-036-0/+645
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| * coolrunner2: Add a few more primitivesRobert Ou2017-06-251-0/+110
| * coolrunner2: Initial mapping of latchesRobert Ou2017-06-254-0/+63
| * coolrunner2: Initial mapping of DFFsRobert Ou2017-06-254-0/+76
| * coolrunner2: Remove redundant INVERT_PTCRobert Ou2017-06-252-4/+1
| * coolrunner2: Remove debug printsRobert Ou2017-06-251-2/+0
| * coolrunner2: Correctly handle $_NOT_ after $sopRobert Ou2017-06-251-5/+41
| * coolrunner2: Also construct the XOR cell in the macrocellRobert Ou2017-06-252-7/+34
| * coolrunner2: Initial techmapping for $sopRobert Ou2017-06-254-153/+268
| * coolrunner2: Initial commitRobert Ou2017-06-243-0/+223
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