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* Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* Merge pull request #793 from whitequark/proc_clean_fix_fully_defClifford Wolf2019-01-191-1/+7
|\ | | | | proc_clean: fix fully def check to consider compare/signal length
| * proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
|/ | | | Fixes #790.
* Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SF2 IO buffer insertionClifford Wolf2019-01-176-3/+171
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #788 from whitequark/masterClifford Wolf2019-01-151-5/+17
|\ | | | | Document $tribuf and some gates
| * manual: document some gates.whitequark2019-01-141-9/+11
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| * manual: explain $tribuf cell.whitequark2019-01-141-0/+10
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* | Merge pull request #787 from whitequark/flowmap_relaxClifford Wolf2019-01-157-35/+776
|\ \ | |/ |/| flowmap: implement depth relaxation
| * flowmap: clean up terminology.whitequark2019-01-081-17/+18
| | | | | | | | | | | | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
| * flowmap: implement depth relaxation.whitequark2019-01-087-22/+762
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* | Improve igloo2 exampleClifford Wolf2019-01-084-5/+29
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typo in manualClifford Wolf2019-01-071-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in $memrd sharingClifford Wolf2019-01-071-2/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #782 from whitequark/flowmap_dfsClifford Wolf2019-01-073-124/+243
|\ | | | | flowmap: construct a max-volume max-flow min-cut, not just any one
| * flowmap: construct a max-volume max-flow min-cut, not just any one.whitequark2019-01-061-7/+10
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| * flowmap: add -minlut option, to allow postprocessing with opt_lut.whitequark2019-01-041-7/+21
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| * flowmap: cleanup for clarity. NFCI.whitequark2019-01-043-107/+179
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| * flowmap: improve debug graph output. NFC.whitequark2019-01-041-47/+76
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| * flowmap: add link to longer version of paper. NFC.whitequark2019-01-041-2/+3
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* | Switch "bugpoint" from system() to run_command()Clifford Wolf2019-01-071-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #783 from whitequark/bugpointClifford Wolf2019-01-072-1/+370
|\ \ | | | | | | bugpoint: new pass
| * | bugpoint: new pass.whitequark2019-01-072-1/+370
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical use of `bugpoint` would involve a script with a pass under test, e.g.: flowmap -relax -optarea 100 and would be invoked as: bugpoint -yosys ./yosys -script flowmap.ys -clean -cells This replaces the current design with the minimal design that still crashes the `flowmap.ys` script. `bugpoint` can also be used to perform generic design minimization using `select`, e.g. the following script: select i:* %x t:$_MUX_ %i -assert-max 0 would remove all parts of the design except for an unbroken path from an input to an output port that goes through exactly one $_MUX_ cell. (The condition is inverted.)
* | Merge pull request #780 from phire/rename_from_wireClifford Wolf2019-01-061-0/+66
|\ \ | | | | | | Rename cells based on the wires they drive.
| * | Rename cells based on the wires they drive.Scott Mansell2019-01-061-0/+66
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* | | Add skeleton Yosys-Libero igloo2 example projectClifford Wolf2019-01-055-0/+44
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\ \ | | | | | | Fix cells_sim.v for Achronix FPGA
| * | Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
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* | Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #776 from mmicko/unify_noflattenClifford Wolf2019-01-044-8/+16
|\ \ | | | | | | Unify usage of noflatten among architectures
| * | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* / Update Verific default pathClifford Wolf2019-01-041-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #775 from whitequark/opt_flowmapClifford Wolf2019-01-033-1/+875
|\ | | | | flowmap: new techmap pass
| * flowmap: new techmap pass.whitequark2019-01-033-1/+875
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* | Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-023-97/+178
|\ \ | |/ |/| opt_expr: refactor and improve simplification of comparisons
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-022-70/+65
| | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs.
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-022-31/+42
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| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-022-32/+40
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| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-023-17/+84
| | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
* | Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ \ | | | | | | anlogic: implement DRAM initialization
| * | anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2019-01-0211-35/+256
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| * \ \ Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-023-17/+45
| |\ \ \ | | | | | | | | | | Initialization of Anlogic DFFs
| | * | | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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