aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
| | | | | | This greatly improves debug information coverage. Fixes #2500.
* Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841whitequark2021-07-161-1/+1
|\ | | | | cxxrtl: don't mark buffered internal wires as UNUSED for debug
| * cxxrtl: don't mark buffered internal wires as UNUSED for debug.whitequark2021-07-161-1/+1
|/ | | | | | | | | | Public wires may alias buffered internal wires, so keep BUFFERED wires in debug information even if they are private. Debug items are only created for public wires, so this does not otherwise affect how debug information is emitted. Fixes #2540. Fixes #2841.
* Merge pull request #2870 from whitequark/cxxrtl-fix-2739whitequark2021-07-161-4/+6
|\ | | | | cxxrtl: mark dead local wires as unused even with inlining disabled
| * cxxrtl: mark dead local wires as unused even with inlining disabled.whitequark2021-07-151-4/+6
| | | | | | | | Fixes #2739.
* | sv: fix two struct access bugsZachary Snow2021-07-155-1/+102
|/ | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* Add a test for interfaces on modules loaded on-demandRupert Swarbrick2021-07-145-2/+48
|
* Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
| | | | | | | | | | I think the code is now a bit easier to follow (and has lost some levels of indentation!). The only non-trivial change is that I removed the check for cell->type[0] != '$' when deciding whether to complain if we couldn't find a module. This will always be true because of the early exit earlier in the function.
* Merge pull request #2866 from rswarbrick/found-initwhitequark2021-07-141-3/+0
|\ | | | | Delete unused found_init variable
| * Delete unused found_init variableRupert Swarbrick2021-07-141-3/+0
|/ | | | | | | Spotted during compilation: passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’: passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-133-1/+84
| | | | | | | While this helper is already useful to squash sequential initializations into one in cxxrtl, its main purpose is to squash overlapping masked memory initializations (when they land) and avoid having to deal with them in cxxrtl runtime.
* Add support for the Bitwuzla solverGCHQDeveloper5602021-07-121-5/+5
|
* kernel/mem: Use delayed removal for inits as well.Marcelina Kościelnicka2021-07-122-4/+20
|
* kernel/mem: Add documentation for more helper functions.Marcelina Kościelnicka2021-07-121-0/+34
|
* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
|
* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
|
* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
|
* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
| | | | | This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
* kernel/mem: Commit new values of attributes in emit.Marcelina Kościelnicka2021-07-121-0/+4
|
* kernel/mem: Make the Mem helpers inherit from AttrObject.Marcelina Kościelnicka2021-07-121-8/+4
|
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-128-25/+62
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
| | | | Fixes #2061.
* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-092-15/+10
|
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-062-2/+11
|
* ecp5: Add DCSC blackboxgatecat2021-07-061-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #2835 from YosysHQ/verific_commandClaire Xen2021-07-051-0/+61
|\ | | | | Support command files in Verific
| * Add additional helpMiodrag Milanovic2021-07-051-0/+22
| |
| * Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
| |
* | Makefile: allow running multiple sanitizers at onceXiretza2021-07-051-3/+3
| |
* | Makefile: use git/make -C instead of cdXiretza2021-07-051-3/+3
| |
* | Makefile: pass PRETTY=0 to ABCXiretza2021-07-051-1/+1
| |
* | Makefile: don't bake DESTDIR into libyosys DT_SONAMEXiretza2021-07-051-2/+2
| | | | | | | | | | | | DESTDIR is only used as a temporary destination for installed files before they are packaged into an archive; the "real" installed location is determined by PREFIX/{BIN,LIB,DAT}DIR.
* | Makefile: clean up PYOSYS configurationXiretza2021-07-051-34/+10
| |
* | Merge pull request #2842 from whitequark/fix-wasi-buildwhitequark2021-06-191-1/+1
|\ \ | | | | | | Fix WASI build after commit 1d88bea1
| * | Fix WASI build after commit 1d88bea1.whitequark2021-06-191-1/+1
|/ /
* | Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigintMiodrag Milanović2021-06-181-0/+2
|\ \ | | | | | | pyosys: Clear SIGINT handler after Python loads
| * | pyosys: Clear SIGINT handler after Python loadsgatecat2021-06-161-0/+2
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | | | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* | sv: fix up end label checkingZachary Snow2021-06-167-7/+98
| | | | | | | | | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* | Include blif reader header in public facing extension header files.Ashton Snelgrove2021-06-161-0/+1
|/
* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
|
* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
|
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
|
* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
|
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* macos: fix leak in proc_self_dirname()Zachary Snow2021-06-141-1/+3
|
* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
| | | | | No change in behaviour, but use range-based for loops instead of iterators.
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
|
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-31 16:23:02 +0000