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* Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
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* Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* Disable $dffeEddie Hung2019-08-081-8/+8
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* INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-0852-562/+1165
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| * Fix compile errorEddie Hung2019-08-071-2/+2
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| * Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
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| * Do not SigSpec::extract() beyond boundsEddie Hung2019-08-072-8/+10
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| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0749-552/+1134
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| | * Merge pull request #1248 from YosysHQ/eddie/abc9_speedupEddie Hung2019-08-074-40/+48
| | |\ | | | | | | | | abc9: speedup by using using "clean" more efficiently
| | | * Add commentEddie Hung2019-08-071-2/+3
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| | | * Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | | | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
| | | * Add TODOEddie Hung2019-08-071-0/+2
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| | | * Compute box_lookup just onceEddie Hung2019-08-071-8/+24
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| | | * Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
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| | | * Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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| | * Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
| | |\ | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr
| | | * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-075-3/+226
| | |\ \ | | | | | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| | | * | Add signed opt_expr testsEddie Hung2019-08-061-0/+50
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| | | * | Add signed testEddie Hung2019-08-061-0/+26
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| | | * | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
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| | | * | Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
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| | | * | Restore original SigSpec::extract()Eddie Hung2019-08-061-1/+1
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| | | * | Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
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| | | * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-0656-172/+763
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| | | * | | Try and fix againEddie Hung2019-07-191-5/+4
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| | * | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-072-94/+206
| | |\ \ \ \ | | | | | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
| | | * | | | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-312-94/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
| | | * | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-3021-32/+164
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| | | * \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-24199-1214/+9423
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| | * | \ \ \ \ \ Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
| | |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | anlogic : Fix alu mapping
| | | * | | | | | | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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| | * | | | | | | | Merge pull request #1252 from YosysHQ/clifford/fix1231Clifford Wolf2019-08-071-15/+2
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | Fix handling of functions/tasks without top-level begin-end block
| | | * | | | | | | | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | Merge pull request #1253 from YosysHQ/clifford/checkClifford Wolf2019-08-073-9/+17
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Be less aggressive with running design->check()
| | | * | | | | | | | | Be less aggressive with running design->check()Clifford Wolf2019-08-063-9/+17
| | | |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | Merge pull request #1257 from YosysHQ/clifford/cellcostsClifford Wolf2019-08-073-109/+103
| | |\ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|/ | | |/| | | | | | | | Redesign of cell cost API
| | | * | | | | | | | Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-072-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | | | | | | | Redesign of cell cost APIClifford Wolf2019-08-072-93/+97
| | | | |_|_|_|_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | Update CHANGELOGDavid Shah2019-08-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-072-36/+71
| | |\ \ \ \ \ \ \ \ | | | |/ / / / / / / | | |/| | | | | | | Improved JSON attr/param encoding
| | | * | | | | | | Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | | | | | | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | Merge pull request #1232 from YosysHQ/dave/write_gzipDavid Shah2019-08-064-7/+79
| | |\ \ \ \ \ \ \ \ | | | |_|/ / / / / / | | |/| | | | | | | Add support for writing gzip-compressed files
| | | * | | | | | | Add test for writing gzip-compressed filesDavid Shah2019-08-062-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * | | | | | | Add support for writing gzip-compressed filesDavid Shah2019-08-062-7/+61
| | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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