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-rw-r--r--tests/opt/opt_ff.v21
-rw-r--r--tests/opt/opt_ff.ys3
-rw-r--r--tests/simple/hierdefparam.v2
-rw-r--r--tests/various/hierarchy.sh59
-rwxr-xr-xtests/various/run-test.sh10
5 files changed, 94 insertions, 1 deletions
diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v
new file mode 100644
index 000000000..a01b64b61
--- /dev/null
+++ b/tests/opt/opt_ff.v
@@ -0,0 +1,21 @@
+module top(
+ input clk,
+ input rst,
+ input [2:0] a,
+ output [1:0] b
+);
+ reg [2:0] b_reg;
+ initial begin
+ b_reg <= 3'b0;
+ end
+
+ assign b = b_reg[1:0];
+ always @(posedge clk or posedge rst) begin
+ if(rst) begin
+ b_reg <= 3'b0;
+ end else begin
+ b_reg <= a;
+ end
+ end
+endmodule
+
diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys
new file mode 100644
index 000000000..704c7acf3
--- /dev/null
+++ b/tests/opt/opt_ff.ys
@@ -0,0 +1,3 @@
+read_verilog opt_ff.v
+synth_ice40
+ice40_unlut
diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v
index ff92c38bd..c9368ca7a 100644
--- a/tests/simple/hierdefparam.v
+++ b/tests/simple/hierdefparam.v
@@ -1,3 +1,5 @@
+`default_nettype none
+
module hierdefparam_top(input [7:0] A, output [7:0] Y);
generate begin:foo
hierdefparam_a mod_a(.A(A), .Y(Y));
diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
new file mode 100644
index 000000000..d33a247be
--- /dev/null
+++ b/tests/various/hierarchy.sh
@@ -0,0 +1,59 @@
+#!/usr/bin/env bash
+# Simple test of hierarchy -auto-top.
+
+set -e
+
+echo -n " TOP first - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
+ read_verilog << EOV
+ module TOP(a, y);
+ input a;
+ output [31:0] y;
+
+ aoi12 p [31:0] (a, y);
+ endmodule
+
+ module aoi12(a, y);
+ input a;
+ output y;
+ assign y = ~a;
+ endmodule
+ EOV
+ hierarchy -auto-top
+EOY
+
+echo -n " TOP last - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
+ read_verilog << EOV
+ module aoi12(a, y);
+ input a;
+ output y;
+ assign y = ~a;
+ endmodule
+
+ module TOP(a, y);
+ input a;
+ output [31:0] y;
+
+ aoi12 foo (a, y);
+ endmodule
+ EOV
+ hierarchy -auto-top
+EOY
+
+echo -n " no explicit top - "
+../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
+ read_verilog << EOV
+ module aoi12(a, y);
+ input a;
+ output y;
+ assign y = ~a;
+ endmodule
+
+ module noTop(a, y);
+ input a;
+ output [31:0] y;
+ endmodule
+ EOV
+ hierarchy -auto-top
+EOY
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 67e1beb23..d49553ede 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -1,6 +1,14 @@
-#!/bin/bash
+#!/usr/bin/env bash
set -e
for x in *.ys; do
echo "Running $x.."
../../yosys -ql ${x%.ys}.log $x
done
+# Run any .sh files in this directory (with the exception of the file - run-test.sh
+shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
+if [ "$shell_tests" ]; then
+ for s in $shell_tests; do
+ echo "Running $s.."
+ bash $s
+ done
+fi