9 files changed, 29 insertions, 34 deletions
diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v
new file mode 100644
index 000000000..a01b64b61
--- /dev/null
+++ b/tests/opt/opt_ff.v
@@ -0,0 +1,21 @@
+module top(
+    input clk,
+    input rst,
+    input [2:0] a,
+    output [1:0] b
+);
+    reg [2:0] b_reg;
+    initial begin
+        b_reg <= 3'b0;
+    end
+
+    assign b = b_reg[1:0];
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+            b_reg <= 3'b0;
+        end else begin
+            b_reg <= a;
+        end
+    end
+endmodule
+
diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys
new file mode 100644
index 000000000..704c7acf3
--- /dev/null
+++ b/tests/opt/opt_ff.ys
@@ -0,0 +1,3 @@
+read_verilog opt_ff.v
+synth_ice40
+ice40_unlut
diff --git a/tests/opt/opt_rmdff_sat.v b/tests/opt/opt_ff_sat.v
index 5a0a6fe37..5a0a6fe37 100644
--- a/tests/opt/opt_rmdff_sat.v
+++ b/tests/opt/opt_ff_sat.v
diff --git a/tests/opt/opt_rmdff_sat.ys b/tests/opt/opt_ff_sat.ys
index 1c3dd9c05..4e7cc6ca4 100644
--- a/tests/opt/opt_rmdff_sat.ys
+++ b/tests/opt/opt_ff_sat.ys
@@ -1,4 +1,4 @@
-read_verilog opt_rmdff_sat.v
+read_verilog opt_ff_sat.v
 prep -flatten
 opt_rmdff -sat
 synth
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index a9fccbb62..59b12c351 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,2 +1,4 @@
 read_verilog opt_lut.v
-equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40
+synth_ice40
+ice40_unlut
+equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
diff --git a/tests/opt/opt_expr.ys b/tests/various/opt_expr.ys
index 0c61ac881..0c61ac881 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/various/opt_expr.ys
diff --git a/tests/opt/opt_rmdff.v b/tests/various/opt_rmdff.v
index b1c06703c..b1c06703c 100644
--- a/tests/opt/opt_rmdff.v
+++ b/tests/various/opt_rmdff.v
diff --git a/tests/opt/opt_rmdff.ys b/tests/various/opt_rmdff.ys
index 081f81782..081f81782 100644
--- a/tests/opt/opt_rmdff.ys
+++ b/tests/various/opt_rmdff.ys
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index 2e0812c48..4257292f5 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -36,6 +36,7 @@ design -save gold
 opt_expr
 wreduce
 
+dump
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate
@@ -45,35 +46,3 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
-
-##########
-
-# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb
-design -reset
-read_verilog <<EOT
-module top(
-    input clk,
-    input rst,
-    input [2:0] a,
-    output [1:0] b
-);
-    reg [2:0] b_reg;
-    initial begin
-        b_reg <= 3'b0;
-    end
-
-    assign b = b_reg[1:0];
-    always @(posedge clk or posedge rst) begin
-        if(rst) begin
-            b_reg <= 3'b0;
-        end else begin
-            b_reg <= a;
-        end
-    end
-endmodule
-EOT
-
-proc
-wreduce
-
-select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i