diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/gowin/init-error.ys | 5 | ||||
| -rw-r--r-- | tests/arch/gowin/init.ys | 16 |
2 files changed, 8 insertions, 13 deletions
diff --git a/tests/arch/gowin/init-error.ys b/tests/arch/gowin/init-error.ys new file mode 100644 index 000000000..de3813d6f --- /dev/null +++ b/tests/arch/gowin/init-error.ys @@ -0,0 +1,5 @@ +read_verilog init.v +chparam -set INIT 0 myDFF*P* +hierarchy -top myDFFP +logger -expect error "unsupported initial value and async reset value combination" 1 +synth_gowin diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys index 4d8e442ac..88e88c15a 100644 --- a/tests/arch/gowin/init.ys +++ b/tests/arch/gowin/init.ys @@ -35,10 +35,10 @@ design -load read # these should synth to a flop with reset chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE -# async should give a warning +# async would give an error # sync should synth to a mux -chparam -set INIT 0 myDFF*S* myDFF*P* -chparam -set INIT 1 myDFF*R* myDFF*C* +chparam -set INIT 0 myDFF*S* +chparam -set INIT 1 myDFF*R* proc flatten @@ -66,13 +66,3 @@ select -assert-count 0 t:DFFRE select -assert-count 2 t:DFFS select -assert-count 2 t:DFFSE select -assert-count 12 t:LUT2 - -# Remove all whiteboxes so we don't inadvertently -# count init attributes inside them -# Should be superseded by https://github.com/YosysHQ/yosys/pull/1949 -delete A:whitebox=1 - -# check the expected leftover init values -# this would happen if your reset value is not the initial value -# which would be weird -select -assert-count 8 a:init |