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-rw-r--r--tests/opt/opt_ff_sat.v25
-rw-r--r--tests/opt/opt_ff_sat.ys1
2 files changed, 12 insertions, 14 deletions
diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v
index fc1e61980..5a0a6fe37 100644
--- a/tests/opt/opt_ff_sat.v
+++ b/tests/opt/opt_ff_sat.v
@@ -1,15 +1,12 @@
-module top(
- input clk,
- input a,
- output b
- );
- reg b_reg;
- initial begin
- b_reg <= 0;
- end
-
- assign b = b_reg;
- always @(posedge clk) begin
- b_reg <= a && b_reg;
- end
+module top (
+ input clk,
+ output reg [7:0] cnt
+);
+ initial cnt = 0;
+ always @(posedge clk) begin
+ if (cnt < 20)
+ cnt <= cnt + 1;
+ else
+ cnt <= 0;
+ end
endmodule
diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys
index 13e4ad29b..4e7cc6ca4 100644
--- a/tests/opt/opt_ff_sat.ys
+++ b/tests/opt/opt_ff_sat.ys
@@ -2,3 +2,4 @@ read_verilog opt_ff_sat.v
prep -flatten
opt_rmdff -sat
synth
+select -assert-count 5 t:$_DFF_P_