diff options
Diffstat (limited to 'tests/xilinx_ug901/rams_sp_rf_rst.ys')
| -rw-r--r-- | tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/xilinx_ug901/rams_sp_rf_rst.ys b/tests/xilinx_ug901/rams_sp_rf_rst.ys new file mode 100644 index 000000000..57e4df9f5 --- /dev/null +++ b/tests/xilinx_ug901/rams_sp_rf_rst.ys @@ -0,0 +1,28 @@ +read_verilog rams_sp_rf_rst.v +hierarchy -top rams_sp_rf_rst +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd rams_sp_rf_rst +stat +#Vivado synthesizes 1 RAMB18E1. + +select -assert-count 1 t:BUFG +select -assert-count 16 t:FDRE +select -assert-count 5 t:LUT2 +select -assert-count 4 t:LUT3 +select -assert-count 13 t:LUT4 +select -assert-count 23 t:LUT5 +select -assert-count 32 t:LUT6 +select -assert-count 128 t:RAM128X1D + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D |