aboutsummaryrefslogtreecommitdiffstats
path: root/tests/xilinx_ug901/rams_sp_nc.ys
diff options
context:
space:
mode:
Diffstat (limited to 'tests/xilinx_ug901/rams_sp_nc.ys')
-rw-r--r--tests/xilinx_ug901/rams_sp_nc.ys22
1 files changed, 0 insertions, 22 deletions
diff --git a/tests/xilinx_ug901/rams_sp_nc.ys b/tests/xilinx_ug901/rams_sp_nc.ys
deleted file mode 100644
index 9b7d6386f..000000000
--- a/tests/xilinx_ug901/rams_sp_nc.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_sp_nc.v
-hierarchy -top rams_sp_nc
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_nc
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 2 t:LUT2
-select -assert-count 1 t:RAMB18E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D