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-rw-r--r--tests/xilinx_ug901/ram_simple_dual_one_clock.v25
1 files changed, 0 insertions, 25 deletions
diff --git a/tests/xilinx_ug901/ram_simple_dual_one_clock.v b/tests/xilinx_ug901/ram_simple_dual_one_clock.v
deleted file mode 100644
index 3390e2da5..000000000
--- a/tests/xilinx_ug901/ram_simple_dual_one_clock.v
+++ /dev/null
@@ -1,25 +0,0 @@
-// Simple Dual-Port Block RAM with One Clock
-// File: simple_dual_one_clock.v
-
-module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
-
-input clk,ena,enb,wea;
-input [9:0] addra,addrb;
-input [15:0] dia;
-output [15:0] dob;
-reg [15:0] ram [1023:0];
-reg [15:0] doa,dob;
-
-always @(posedge clk) begin
- if (ena) begin
- if (wea)
- ram[addra] <= dia;
- end
-end
-
-always @(posedge clk) begin
- if (enb)
- dob <= ram[addrb];
-end
-
-endmodule \ No newline at end of file