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-rw-r--r--tests/xilinx_ug901/bytewrite_ram_1b.ys22
1 files changed, 0 insertions, 22 deletions
diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys
deleted file mode 100644
index 4f0967801..000000000
--- a/tests/xilinx_ug901/bytewrite_ram_1b.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog bytewrite_ram_1b.v
-hierarchy -top bytewrite_ram_1b
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd bytewrite_ram_1b
-stat
-#Vivado synthesizes 1 RAMB36E1.
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:LUT2
-select -assert-count 8 t:RAMB36E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D