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-rw-r--r--tests/xilinx_ug901/black_box_1.ys15
1 files changed, 0 insertions, 15 deletions
diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys
deleted file mode 100644
index acf0b5761..000000000
--- a/tests/xilinx_ug901/black_box_1.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog black_box_1.v
-hierarchy -top black_box_1
-proc
-tribuf
-flatten
-synth
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd black_box_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 1 black box.
-#stat
-#select -assert-count 0 t:LUT1
-#select -assert-count 1 t:$_TBUF_
-#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D