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Diffstat (limited to 'tests/xilinx/tribuf.ys')
| -rw-r--r-- | tests/xilinx/tribuf.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys new file mode 100644 index 000000000..c9cfb8546 --- /dev/null +++ b/tests/xilinx/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D |