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Diffstat (limited to 'tests/xilinx/mul_unsigned.ys')
| -rw-r--r-- | tests/xilinx/mul_unsigned.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys new file mode 100644 index 000000000..77990bd68 --- /dev/null +++ b/tests/xilinx/mul_unsigned.ys @@ -0,0 +1,10 @@ +read_verilog mul_unsigned.v +proc +hierarchy -top mul_unsigned +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 30 t:FDRE +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D |