diff options
Diffstat (limited to 'tests/xilinx/mul.ys')
| -rw-r--r-- | tests/xilinx/mul.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys new file mode 100644 index 000000000..ec30c9c2c --- /dev/null +++ b/tests/xilinx/mul.ys @@ -0,0 +1,15 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT2 +select -assert-count 1 t:LUT3 +select -assert-count 6 t:LUT4 +select -assert-count 1 t:LUT5 +select -assert-count 33 t:LUT6 +select -assert-count 11 t:MUXCY +select -assert-count 1 t:MUXF7 +select -assert-count 12 t:XORCY +select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D |