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Diffstat (limited to 'tests/xilinx/logic.ys')
| -rw-r--r-- | tests/xilinx/logic.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys new file mode 100644 index 000000000..9ae5993aa --- /dev/null +++ b/tests/xilinx/logic.ys @@ -0,0 +1,11 @@ +read_verilog logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D |