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Diffstat (limited to 'tests/xilinx/div_mod.ys')
| -rw-r--r-- | tests/xilinx/div_mod.ys | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys deleted file mode 100644 index da7e60a9a..000000000 --- a/tests/xilinx/div_mod.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 12 t:LUT1 -select -assert-count 19 t:LUT2 -select -assert-count 13 t:LUT4 -select -assert-count 6 t:LUT5 -select -assert-count 82 t:LUT6 -select -assert-count 65 t:MUXCY -select -assert-count 37 t:MUXF7 -select -assert-count 11 t:MUXF8 -select -assert-count 28 t:XORCY -select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D |