diff options
Diffstat (limited to 'tests/xilinx/div_mod.ys')
| -rw-r--r-- | tests/xilinx/div_mod.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys new file mode 100644 index 000000000..cc00b1a27 --- /dev/null +++ b/tests/xilinx/div_mod.ys @@ -0,0 +1,17 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT1 +select -assert-count 21 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 80 t:LUT6 +select -assert-count 65 t:MUXCY +select -assert-count 36 t:MUXF7 +select -assert-count 9 t:MUXF8 +select -assert-count 28 t:XORCY +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D |