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Diffstat (limited to 'tests/xilinx/add_sub.ys')
| -rw-r--r-- | tests/xilinx/add_sub.ys | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys index 821341f20..f06e7fa01 100644 --- a/tests/xilinx/add_sub.ys +++ b/tests/xilinx/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |