diff options
Diffstat (limited to 'tests/xilinx/add_sub.ys')
| -rw-r--r-- | tests/xilinx/add_sub.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys new file mode 100644 index 000000000..f06e7fa01 --- /dev/null +++ b/tests/xilinx/add_sub.ys @@ -0,0 +1,11 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 14 t:LUT2 +select -assert-count 6 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D + |