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-rw-r--r--tests/various/gen_if_null.v12
-rw-r--r--tests/various/gen_if_null.ys4
2 files changed, 10 insertions, 6 deletions
diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v
index a12ac6288..992bc68b3 100644
--- a/tests/various/gen_if_null.v
+++ b/tests/various/gen_if_null.v
@@ -1,13 +1,17 @@
-module test(x, y, z);
+`default_nettype none
+module test;
localparam OFF = 0;
generate
if (OFF) ;
- else input x;
- if (!OFF) input y;
+ else wire x;
+ if (!OFF) wire y;
else ;
if (OFF) ;
else ;
if (OFF) ;
- input z;
+ wire z;
endgenerate
+ assign genblk1.x = 0;
+ assign genblk2.y = 0;
+ assign z = 0;
endmodule
diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys
index 31dfc444b..0733e3a94 100644
--- a/tests/various/gen_if_null.ys
+++ b/tests/various/gen_if_null.ys
@@ -1,4 +1,4 @@
read_verilog gen_if_null.v
-select -assert-count 1 test/x
-select -assert-count 1 test/y
+select -assert-count 1 test/genblk1.x
+select -assert-count 1 test/genblk2.y
select -assert-count 1 test/z