diff options
Diffstat (limited to 'tests/various/wreduce.ys')
| -rw-r--r-- | tests/various/wreduce.ys | 88 |
1 files changed, 9 insertions, 79 deletions
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index deb99304d..4257292f5 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -1,78 +1,5 @@ - -read_verilog <<EOT -module wreduce_add_test(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -prep # calls wreduce - -select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - read_verilog <<EOT -module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -prep # calls wreduce - -select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) - j; -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -prep # calls wreduce - -select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o); +module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o); assign o = (j >> 4) - i; endmodule EOT @@ -81,7 +8,8 @@ hierarchy -auto-top proc design -save gold -prep # calls wreduce +opt_expr +wreduce select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -96,8 +24,8 @@ sat -verify -prove-asserts -show-ports miter ########## read_verilog <<EOT -module wreduce_sub_test4(input [3:0] i, output [8:0] o); - assign o = 5'b00010 - i; +module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); + assign o = (j >>> 4) - i; endmodule EOT @@ -105,9 +33,11 @@ hierarchy -auto-top proc design -save gold -prep # calls wreduce +opt_expr +wreduce -select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i +dump +select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate |