diff options
Diffstat (limited to 'tests/various/abc9.ys')
| -rw-r--r-- | tests/various/abc9.ys | 38 |
1 files changed, 32 insertions, 6 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 6e2415ad7..ac714665f 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -45,14 +45,16 @@ sat -seq 10 -verify -prove-asserts -show-ports miter design -reset read_verilog -icells <<EOT module abc9_test036(input clk, d, output q); -(* keep *) reg w; -$__ABC9_FF_ ff(.D(d), .Q(w)); -wire \ff.clock = clk; -wire \ff.init = 1'b0; +(* keep, init=1'b0 *) wire w; +$_DFF_P_ ff(.C(clk), .D(d), .Q(w)); assign q = w; endmodule EOT -abc9 -lut 4 -dff +equiv_opt -assert abc9 -lut 4 -dff +design -load postopt +cd abc9_test036 +select -assert-count 1 t:$_DFF_P_ +select -assert-none t:* t:$_DFF_P_ %d design -reset @@ -67,8 +69,32 @@ specify endspecify endmodule -module top(input [1:0] i, output o); +module abc9_test037(input [1:0] i, output o); LUT2 #(.mask(4'b0)) lut (.i(i), .o(o)); endmodule EOT abc9 + + +design -reset +read_verilog -icells <<EOT +module abc9_test038(input clk, output w, x, y, z); +(* init=1'b1 *) wire w; +$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w)); +(* init=1'bx *) wire x; +$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x)); +(* init=1'b0 *) wire y; +$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y)); +(* init=1'b0 *) wire z; +$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z)); +endmodule +EOT +simplemap +equiv_opt abc9 -lut 4 -dff +design -load postopt +cd abc9_test038 +select -assert-count 3 t:$_DFF_N_ +select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D +clean +select -assert-count 2 a:init +select -assert-none w:w w:z %% a:init %D |