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-rw-r--r--tests/techmap/bug2972.ys20
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diff --git a/tests/techmap/bug2972.ys b/tests/techmap/bug2972.ys
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+read_verilog -specify <<EOT
+(* abc9_box, blackbox*)
+module box(input clk, d, output reg q, output do);
+parameter P = 0;
+always @(posedge clk)
+ q <= d;
+assign do = d;
+specify
+ (posedge clk => (q : d)) = 1;
+ (d => do) = 1;
+endspecify
+endmodule
+
+module top(input clk, d, output q);
+box i1(clk, d, q);
+endmodule
+EOT
+hierarchy
+abc9 -lut 4
+abc9 -lut 4