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-rw-r--r--tests/techmap/aigmap.ys10
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diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys
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+read_verilog <<EOT
+module top(input i, j, s, output o, p);
+assign o = s ? j : i;
+assign p = ~i;
+endmodule
+EOT
+
+select t:$mux
+aigmap -select
+select -assert-any %