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-rw-r--r--tests/opt/bug3047.ys12
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/opt/bug3047.ys b/tests/opt/bug3047.ys
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+read_verilog << EOT
+
+module test (A, B, C, D, Y);
+ input A, B, C, D;
+ output Y;
+ assign Y = A^B^C^D^A;
+endmodule
+
+EOT
+
+techmap
+equiv_opt -assert extract_reduce