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-rw-r--r--tests/opt/bug1525.ys13
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys
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+++ b/tests/opt/bug1525.ys
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+read_verilog << EOF
+module top(...);
+input A1, A2, B, S;
+output O;
+
+assign O = S ? (A1 & B) : (A2 & B);
+
+endmodule
+EOF
+
+simplemap
+opt_share
+dump