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-rw-r--r--tests/ice40/adffs.ys17
1 files changed, 10 insertions, 7 deletions
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index aee8cd6b4..14b251c5c 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,9 +1,12 @@
read_verilog adffs.v
proc
-dff2dffe
-synth_ice40
-select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFE
-select -assert-count 4 t:SB_LUT4
-#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D
-write_verilog adffs_synth.v
+async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
+select -assert-count 1 t:SB_DFFN
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 7 t:SB_LUT4
+select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D