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-rw-r--r--tests/efinix/shifter.ys11
1 files changed, 0 insertions, 11 deletions
diff --git a/tests/efinix/shifter.ys b/tests/efinix/shifter.ys
deleted file mode 100644
index 1a6b5565c..000000000
--- a/tests/efinix/shifter.ys
+++ /dev/null
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-read_verilog shifter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 1 t:EFX_GBUFCE
-select -assert-count 8 t:EFX_FF
-select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D