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Diffstat (limited to 'tests/efinix/fsm.ys')
| -rw-r--r-- | tests/efinix/fsm.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys new file mode 100644 index 000000000..9de6aa280 --- /dev/null +++ b/tests/efinix/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 6 t:EFX_FF +select -assert-count 15 t:EFX_LUT4 +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D |