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Diffstat (limited to 'tests/efinix/alu.ys')
| -rw-r--r-- | tests/efinix/alu.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/efinix/alu.ys b/tests/efinix/alu.ys new file mode 100644 index 000000000..0d58a7c8a --- /dev/null +++ b/tests/efinix/alu.ys @@ -0,0 +1,13 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 66 t:EFX_ADD +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 32 t:EFX_FF +select -assert-count 605 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D |