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-rw-r--r--tests/ecp5/rom.ys9
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys
deleted file mode 100644
index 8a52749a1..000000000
--- a/tests/ecp5/rom.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog rom.v
-proc
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 6 t:LUT4
-select -assert-count 3 t:PFUMX
-select -assert-none t:LUT4 t:PFUMX %% t:* %D