1 files changed, 109 insertions, 0 deletions
diff --git a/tests/ecp5/latches_synth.v b/tests/ecp5/latches_synth.v
new file mode 100644
index 000000000..816e10d4d
--- /dev/null
+++ b/tests/ecp5/latches_synth.v
@@ -0,0 +1,109 @@
+/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */
+
+(* top =  1  *)
+(* src = "latches.v:27" *)
+module top(clk, clr, pre, a, b, b1, b2);
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
+  wire _0_;
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *)
+  wire _1_;
+  (* src = "latches.v:31" *)
+  input a;
+  (* src = "latches.v:32" *)
+  output b;
+  (* src = "latches.v:32" *)
+  output b1;
+  (* src = "latches.v:32" *)
+  output b2;
+  (* src = "latches.v:28" *)
+  input clk;
+  (* src = "latches.v:29" *)
+  input clr;
+  (* src = "latches.v:30" *)
+  input pre;
+  (* src = "latches.v:43|latches.v:9" *)
+  wire \u_latchn.d ;
+  (* src = "latches.v:43|latches.v:9" *)
+  wire \u_latchn.en ;
+  (* src = "latches.v:43|latches.v:9" *)
+  wire \u_latchn.q ;
+  (* src = "latches.v:36|latches.v:2" *)
+  wire \u_latchp.d ;
+  (* src = "latches.v:36|latches.v:2" *)
+  wire \u_latchp.en ;
+  (* src = "latches.v:36|latches.v:2" *)
+  wire \u_latchp.q ;
+  (* src = "latches.v:50|latches.v:16" *)
+  wire \u_latchsr.clr ;
+  (* src = "latches.v:50|latches.v:16" *)
+  wire \u_latchsr.d ;
+  (* src = "latches.v:50|latches.v:16" *)
+  wire \u_latchsr.en ;
+  (* src = "latches.v:50|latches.v:16" *)
+  wire \u_latchsr.pre ;
+  (* src = "latches.v:50|latches.v:16" *)
+  wire \u_latchsr.q ;
+  (* module_not_derived = 32'd1 *)
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *)
+  LUT4 #(
+    .INIT(16'h5150)
+  ) _2_ (
+    .A(clr),
+    .B(clk),
+    .C(pre),
+    .D(b2),
+    .Z(_0_)
+  );
+  (* module_not_derived = 32'd1 *)
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *)
+  LUT4 #(
+    .INIT(16'h5554)
+  ) _3_ (
+    .A(clr),
+    .B(clk),
+    .C(pre),
+    .D(b2),
+    .Z(_1_)
+  );
+  (* module_not_derived = 32'd1 *)
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *)
+  PFUMX _4_ (
+    .ALUT(_1_),
+    .BLUT(_0_),
+    .C0(a),
+    .Z(b2)
+  );
+  (* module_not_derived = 32'd1 *)
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
+  LUT4 #(
+    .INIT(16'bx1x1x1x0x0x1x0x0)
+  ) _5_ (
+    .A(1'h0),
+    .B(clk),
+    .C(b),
+    .D(a),
+    .Z(b)
+  );
+  (* module_not_derived = 32'd1 *)
+  (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *)
+  LUT4 #(
+    .INIT(16'bx1x1x0x1x1x0x0x0)
+  ) _6_ (
+    .A(1'h0),
+    .B(clk),
+    .C(b1),
+    .D(a),
+    .Z(b1)
+  );
+  assign \u_latchn.d  = a;
+  assign \u_latchn.en  = clk;
+  assign \u_latchn.q  = b1;
+  assign \u_latchp.d  = a;
+  assign \u_latchp.en  = clk;
+  assign \u_latchp.q  = b;
+  assign \u_latchsr.clr  = clr;
+  assign \u_latchsr.d  = a;
+  assign \u_latchsr.en  = clk;
+  assign \u_latchsr.pre  = pre;
+  assign \u_latchsr.q  = b2;
+endmodule