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-rw-r--r--tests/ecp5/dffs.ys18
1 files changed, 14 insertions, 4 deletions
diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys
index 5510bb440..93b8595ad 100644
--- a/tests/ecp5/dffs.ys
+++ b/tests/ecp5/dffs.ys
@@ -1,9 +1,19 @@
read_verilog dffs.v
-hierarchy -top top
+design -save read
+
proc
-flatten
+hierarchy -top dff
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 2 t:TRELLIS_FF
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file