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-rw-r--r--tests/ecp5/counter.ys9
1 files changed, 4 insertions, 5 deletions
diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys
index c65c21622..8ef70778f 100644
--- a/tests/ecp5/counter.ys
+++ b/tests/ecp5/counter.ys
@@ -2,10 +2,9 @@ read_verilog counter.v
hierarchy -top top
proc
flatten
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 6 t:SB_CARRY
-select -assert-count 8 t:SB_DFFR
-select -assert-count 8 t:SB_LUT4
-select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
+select -assert-count 4 t:CCU2C
+select -assert-count 8 t:TRELLIS_FF
+select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D