1 files changed, 24 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_addbit.v b/tests/asicworld/code_verilog_tutorial_addbit.v
new file mode 100644
index 000000000..22063b052
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_addbit.v
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+module addbit (
+a      , // first input
+b      , // Second input
+ci     , // Carry input
+sum    , // sum output
+co       // carry output
+);
+//Input declaration
+input a;
+input b;
+input ci;
+//Ouput declaration
+output sum;
+output co;
+//Port Data types
+wire  a;
+wire  b;
+wire  ci;
+wire  sum;
+wire  co;
+//Code starts here
+assign {co,sum} = a + b + ci;
+
+endmodule // End of Module addbit