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-rw-r--r--tests/arch/xilinx/latches.ys3
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index e226c2ec8..ee87fee21 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -18,9 +18,8 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad #
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
-select -assert-count 1 t:INV
-select -assert-none t:LDCE t:INV %% t:* %D
+select -assert-none t:LDCE %% t:* %D
design -load read